L-USS820FD-DB 参数 Datasheet PDF下载

Data Sheet, Rev. 1

August 2004

USS-820FD

USB Device Controller

Register Interface

The USS-820FD is controlled through an asynchronous, read/write register interface. Registers are addressed via

the A[4:0] pins, and control is provided through the RDN, WRN, and IOCSN pins. Reserved bits of registers must

always be written with 0. Writing 1 to these bits may produce undefined results. These bits return undefined values

when read.

A register read is accomplished by placing the register address on the A bus and asserting the IOCSN and RDN

pins. After read data valid (tRDDV), the register data will appear on the D bus. A register write is accomplished by

placing the register address on the A bus and the data to be written on the D bus, and asserting the IOCSN and

WRN pins.

Tables 7 and 8 show alphabetical and numerical listings of all the available special function registers (SFR) for the

USS-820FD. For reference purposes, an alphabetized list of SFR bit names is included in Appendix A. Tables 12—

ual, endpoint-specific register is selected by the EPINDEX register.

Table 7. Special Function Registers (By Name)

Register

DSAV

DSAV1

EPCON*

EPINDEX

FADDR

LOCK

MCSR

PEND

REV

RXCNTH

RXCNTL

RXCON

RXDAT

RXFLG

RXSTAT*

SBI*

SBI1*

SBIE

SBIE1

SCR

SCRATCH

SOFH*

SOFL*

SSR*

TXCNTH

TXCNTL

TXCON

TXDAT

TXFLG

TXSTAT

Description

Data Set Available

Data Set Available 1

Endpoint Control Register

Endpoint Index Register

Function Address Register

Suspend Power-Off Locking Register

Miscellaneous Control/Status Register

Pend Hardware Status Update Register

Hardware Revision Register

Receive FIFO Byte-Count High Register

Receive FIFO Byte-Count Low Register

Receive FIFO Control Register

Receive FIFO Data Register

Receive FIFO Flag Register

Endpoint Receive Status Register

Serial Bus Interrupt Register

Serial Bus Interrupt Register 1

Serial Bus Interrupt Enable Register

Serial Bus Interrupt Enable Register 1

System Control Register

Scratch Firmware Information Register

Start of Frame High Register

Start of Frame Low Register

System Status Register

Transmit FIFO Byte-Count High Register

Transmit FIFO Byte-Count Low Register

USB Transmit FIFO Control Register

Transmit FIFO Data Register

Transmit FIFO Flag Register

Endpoint Transmit Status Register

Address

1DH

1EH

0BH

†

0AH

10H

19H

1CH

1AH

18H

07H

†

06H

†

08H

†

05H

†

09H

†

Table

Page

0DH

†

14H

15H

16H

17H

11H

1BH

0FH

0EH

12H

02H

†

01H

†

03H

†

00H

†

04H

†

0CH

†

* Contains shared bits. See Special Firmware Action for Shared Register Bits section.

† Indexed by EPINDEX.

Agere Systems Inc.

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