Revision 1.16 – July 19, 2006
440GR – PPC440GR Embedded Processor
Preliminary Data Sheet
Table 7. Signal Functional Description (Sheet 7 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
System Interface
SysClk
SysErr
Main system clock input.
Set to 1 when a machine check is generated.
Main system reset. External logic can drive this bidirectional
pin low (minimum of 16 cycles) to initiate a system reset. A
system reset can also be initiated by software. Implemented as
an open-drain output (two states; 0 or open circuit).
Halt from external debugger.
Processor timer external input clock.
This signal must be connected to a clock. It can be connected
to any available clocking signal in the frequency range of
32kHz to 100MHz including TmrClk1.
General purpose I/O 0 through 63. To access these functions,
software must set DCR register bits.
Test Enable.
Receiver Inhibit. Active only when TestEn is active.
Mode Control.
Leakage Test.
Reference Enable.
Driver Inhibit. Used for test purposes only. Tie up as specified
in Note 2 for normal operation.
Module characterization and screening.
Clock
O
3.3V LVTTL
3.3V tolerant
2.5V CMOS
3.3V tolerant
2.5V CMOS
3.3V LVTTL
3.3V tolerant
2.5V CMOS
3.3V tolerant
2.5V CMOS
Multiplex
Multiplex
Multiplex
Multiplex
Multiplex
Multiplex
3.3V tolerant
2.5V CMOS
Perf screen
ring osc
2
1, 3
3
Description
I/O
Type
Notes
SysReset
I/O
1, 2
Halt
TmrClk1
I
I
1, 4
TmrClk2
I
GPIO00:63
TestEn
RcvrInh
ModeCtrl
LeakTest
RefEn
DrvrInh1:2
PSROOut
I/O
I
I
I
I
I
I
O
56
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
