R
LOOP
L
LOOP
ζ
=
R
LOOP
C
GATE
≥
1
2
L
LOOP
V
PULSE
C
GATE
∴
R
LOOP
L
LOOP
≥
2
C
GATE
As shown, minimizing L
LOOP
needed for critical
minimizes the value of R
LOOP
dampening. Minimizing L
LOOP
also minimizes the rise/fall time. Therefore, it is
strongly recommended that the gate drive be located as close to the SiC MOSFET
MOSFET is
5 Ω.
as possible to minimize L
LOOP
.
The internal gate resistance of the SiC
An external resistance of 6.8 Ω was used to characterize this device.
�½
Lower values of external gate resistance can be used so long as the gate fidelity is
maintained. In the event that no external gate resistance is used, it is suggested
that the gate current be checked to indirectly verify that there is no ringing present
in the gate circuit. This can be accomplished with a very small current transformer.
A recommended setup is a two-stage current transformer as shown below:
IG SENSE
VCC
GATE DRIVER
GATE DRIVE INPUT
+
-
VEE
T1
SiC DMOSFET
5
CMF20120D Rev. -
CREE [ CREE, INC ]
