Stray inductance on source lead causes load
di/dt to be fed back into gate drive which
causes the following:
• Switch di/dt is limited
• Could cause oscillation
LOAD CURRENT
Kelvin gate connection with separate
source return is highly recommended
20V
20V
R GATE
DRIVE
R GATE
SiC DMOS
DRIVE
SiC DMOS
L STRAY
LOAD CURRENT
L STRAY
A schematic of the gate driver circuit used for characterization of the SiC MOSFET
is shown below:
+VCC
+VCC
THESE COMPONENTS ARE
LOCATED ON THE -VEE
PLANE
C1
10u
-VEE
C2
100n
-VEE
C4
100n
-VEE
C5
100n
-VEE
C8
THESE COMPONENTS ARE
LOCATED ON THE GND
PLANE
C3
10u
GND
+VCC
C6
10u
-VEE
-VEE
1
C10
100n
R1
+VCC
U1
LM2931T-5.0
IN
GND
OUT
3
C11
100u
6.3V
100n
R2
390
10n
ISO1
R4
1
2
R5
120
R6
120
330
3
3
C14
5
6N137
100n
-VEE
-VEE
4
2
8
1
7
6
2
U2
VCC
IN
NC
GND
IXDI414
-VEE
VCC
OUT
OUT
GND
8
7
6
5
-VEE
C13
1
10u
C9
C7
PIN 1 SOURCE
100n
-VEE
C12
100n
-VEE
R3
TBD 1206
RB160M-60
R7
TBD 1206
R8
TBD 1206
C15
100n
-VEE
C16
100n
-VEE
C17
100n
-VEE
C18
100n
-VEE
C19
100n
-VEE
C20
10u
-VEE
RB160M-60
J2
BNC
D2
D1
PIN 2 GATE
PULSE GEN INPUT
J1
BNC
2
VGS MONITOR
2
1
The gate driver is an IXYS IXDI414. This device has a 35 V ouput swing, output
resistance of 0.6 Ω typical, and a peak current capability of 14 A. The external
�½
gate resistance used for characterization of the SiC MOSFET was 6.8 Ω. Careful
consideration needs to be given to the selection of the gate driver. The typical
application error is selection of a gate driver that has adequate swing, but output
6
CMF20120D Rev. -
CREE [ CREE, INC ]
