CY7C4421/4201/4211/4221
CY7C4231/4241/4251
Switching Waveforms
(continued)
Full Flag Timing
NO Write
WCLK
t
SKEW1
D
0
–D
8
t
WFF
FF
t
DS
DATA Write
t
WFF
t
WFF
t
SKEW1
DATA Write
NO Write
NO Write
WEN1
WEN2
(if applicable)
RCLK
t
ENS
t
ENH
t
ENS
t
ENH
REN1,
REN2
OE
LOW
t
A
t
A
DATA Read
NEXT DATA Read
Q
0
–Q
8
DATA IN OUTPUT REGISTER
Programmable Almost Empty Flag Timing
t
CLKH
WCLK
t
ENS
t
ENH
WEN1
WEN2
(if applicable)
t
ENS
t
ENH
PAE
t
SKEW2[22]
RCLK
t
ENS
REN1,
REN2
Notes:
22. t
SKEW2
is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of
WCLK and the rising RCLK is less than t
SKEW2
, then PAE may not change state until the next RCLK.
23. PAE offset = n.
24. If a Read is performed on this rising edge of the Read clock, there will be Empty + (n – 1) words in the FIFO when PAE goes LOW.
t
CLKL
Note
t
PAE
N + 1 WORDS
INFIFO
Note
t
PAE
t
ENS
t
ENH
Document #: 38-06016 Rev. *C
Page 12 of 19
CYPRESS [ CYPRESS SEMICONDUCTOR ]
