Block Diagram
2
Block Diagram
The superset device in the MCF5275 family comes in a 256 Mold Array Plastic Ball Grid Array
(MAPBGA) package.
Figure 1 shows a top-level block diagram of the MCF5275, the superset device.
EIM
DDR
CHIP
SELECTS
(To/From SRAM backdoor)
QSPI
I2C_SDA
I2C_SCL
TXDx
EBI
INTC0 INTC1
RXDx
Arbiter
RTSx
CTSx
DTOUTx
DTINx
FAST ETHERNET
CONTROLLER
(FEC0)
(To/From PADI)
(To/From PADI)
FEC0
FEC1
USB
UART
0
UART UART
I2C
QSPI
FAST ETHERNET
CONTROLLER
(FEC1)
1
2
SDRAMC
PWMx
D[31:16]
A[23:0]
DTIM
3
DTIM DTIM
DTIM
0
1
2
(To/From
PADI)
R/
W
4 CH DMA
DREQ[1:0]
CS[3:0]
TA
JTAG_EN
TRST
V2 ColdFire CPU
DACK[3:0]
JTAG
TAP
TCLK
EMAC
DIV
TMS
TDI
TDO
JTAG_EN
TSIZ[1:0]
TEA
64 Kbytes
SRAM
(8Kx16)x4
(To/From
PADI)
16 Kbytes
CACHE
(1Kx32)x4
BS[3:2]
4 CH PWM
(To/From PADI)
PORTS
(GPIO)
CIM
Watchdog
Timer
(To/From Arbiter backdoor)
PLL
CLKGEN
USB 2.0
Full Speed
PIT0
PIT1
PIT2
PIT3
Edge
Port
MDHA
RNGA
SKHA
Cryptography
Modules
(To/From INTC)
(To/From PADI)
Figure 1. MCF5275 Block Diagram
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2
Freescale Semiconductor
3
Preliminary—Subject to Change Without Notice
FREESCALE [ Freescale ]
