HANBit
HSD8M64D4B
SIMPLIFIED TRUTH TABLE
COMMAND
Register
Mode register set
Auto refresh
Refresh
Self
refres
h
Auto
disable
Auto
disable
Auto
disable
Auto
disable
Burst Stop
Precharg
e
Bank selection
All banks
Entry
Exit
Entry
Exit
H
H
H
L
H
L
H
H
X
H
L
X
X
L
H
L
H
L
L
H
L
X
H
L
H
L
L
L
X
V
X
X
H
X
V
X
X
H
X
H
X
H
H
H
X
V
X
X
H
X
V
L
L
X
V
X
X
H
X
V
X
X
X
X
X
X
X
V
X
X
X
7
V
X
L
H
X
precharge
precharge
H
X
L
H
L
L
X
V
H
X
X
precharge
Entry
Exit
CKE
n-1
H
H
L
H
CKE
N
X
H
L
H
X
/C
S
L
L
L
H
L
/R
A
S
L
L
H
X
L
/C
A
S
L
L
H
X
H
/W
E
L
H
H
X
H
D
Q
M
X
X
X
X
V
BA
0,1
A10/
AP
OP code
X
X
Row address
L
H
X
L
H
L
H
X
V
H
Column
Address
(A0 ~ A7)
Column
L
Address
(A0 ~ A7)
4,5
6
4
4,5
4
A11
A9~A0
NOTE
1,2
3
3
3
3
Bank active & row addr.
Read &
column
address
precharge
Write &
column
address
Clock suspend or
active power down
Precharge
down mode
DQM
power
No operation command
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
Notes :
1. OP Code : Operand code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
URL:www.hbe.co.kr
REV.1.0 (August.2002)
HANBit Electronics Co.,Ltd
9
HANBIT [ HANBIT ELECTRONICS CO.,LTD ]
