ICS9250-27
Frequency Generator and Integrated Buffers for Celeron & PII/IIITM
Absolute Maximum Ratings
Core Supply Voltage
I/O Supply Voltage
4.6 V
3.6V
Logic Inputs
GND –0.5 V to VDD +0.5 V
0°C to +70°C
–65°C to +150°C
Ambient Operating Temperature
Storage Temperature
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, VDDL = 2.5 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
VIH
CONDITIONS
MIN
2
TYP
MAX
VDD+0.3
0.8
UNITS
V
VIL
VSS-0.3
-5
V
IIH
VIN = VDD
5
µA
IIL1
VIN = 0 V; Inputs with no pull-up resistors
VIN = 0 V; Inputs with pull-up resistors
CL = 0 pF; Select @ 66 MHz
-5
2
-100
97
Input Low Current
µA
IIL2
-200
115
110
165
330
320
395
19
CL = 0 pF; Select @ 100 MHz
91
mA
CL = 0 pF; Select @ 133 MHz
100
295
280
300
16
IDD3.3OP
CL = Max loads; Select @ 66 MHz
CL = Max loads; Select @ 100 MHz
CL = Max loads; Select @ 133 MHz
CL = 0 pF; Select @ 66 MHz
mA
mA
mA
Operating Supply
Current
CL = 0 pF; Select @ 100 MHz
25
35
CL = 0 pF; Select @ 133 MHz
26
40
IDD2.5OP
CL = Max loads; Select @ 66 MHz
CL = Max loads; Select @ 100 MHz
19
30
34
50
CL = Max loads; Select @ 133 MHz
CL = Max loads
40
220
<1
14.318
7
70
400
10
IDD3.3PD
IDD.25PD
Fi
Powerdown Current
A
µ
Input address VDD or GND
VDD = 3.3 V
Input Frequency
Pin Inductance
12
27
16
MHz
nH
pF
Lpin
CIN
Logic Inputs
5
Input Capacitance1
COUT
CINX
Ttrans
Ts
Output pin capacitance
X1 & X2 pins
6
pF
45
5
pF
Transition time1
Settling time1
Clk Stabilization1
To 1st crossing of target frequency
From 1st crossing to 1% target frequency
ms
ms
5
TSTAB
tPZH,tPZL
tPHZ,tPLZ
From VDD = 3.3 V to 1% target frequency
Output enable delay (all outputs)
Output disable delay (all outputs)
5
ms
ns
ns
1
1
10
10
Delay1
1Guaranteed by design, not 100% tested in production.
IDTTM Frequency Generator and Integrated Buffers for Celeron & PII/IIITM
0395F—01/25/10
7
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
