ICS9250-27
Frequency Generator and Integrated Buffers for Celeron & PII/III
TM
Power Down Waveform
Note
1.
After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2.
Power-up latency <3ms.
3.
Waveform shown for 100MHz
Maximum Allowed Current
815
Condition
Powerdown Mode
(PWRDWN# = 0
Full Active 66MHz
FS[2:0] = 010
Full Active 100MHz
FS[2:0] = 011
Full Active 133MHz
FS[2:0] = 111
Max 2.5V supply consumption
Max discrete cap loads,
Vddq2 = 2.625V
All static inputs = Vddq3 or GND
10mA
70mA
100mA
Max 2.5V supply consumption
Max discrete cap loads,
Vddq2 = 3.465V
All static inputs = Vddq3 or GND
10mA
280mA
280mA
Clock Enable Configuration
PD#
0
1
CPUCLK
LOW
ON
SDRAM
LOW
ON
IOAPIC
LOW
ON
66MHz
LOW
ON
PCICLK
LOW
ON
REF,
48MHz
LOW
ON
Osc
OF F
ON
VCOs
OFF
ON
IDT
TM
Frequency Generator and Integrated Buffers for Celeron & PII/III
TM
0395F—01/25/10
3
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
