ICS9250-27
Frequency Generator and Integrated Buffers for Celeron & PII/IIITM
Byte 2: Control Register
(1 = enable, 0 = disable)
Bit
Pin#
9
Name
3V66-2 (AGP)
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Undefined bit
PWD
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
1
1
1
1
1
X
20
19
18
16
15
13
-
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
3. Undefined bit can be wirtten with either a "1" or "0".
Byte 3: ICS Reserved Functionality and frequency select register (Default as noted in PWD)
Bit
Desctiption
PWD
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
ICS Reserved bit (Note 2)
ICS Reserved bit (Note 2)
ICS Reserved bit (Note 2)
ICS Reserved bit (Note 2)
ICS Reserved bit (Note 2)
Undefined bit (Note 3)
0
0
0
0
0
X
X
Undefined bit (Note 3)
CPUCLK SDRAM 3V66 PCICLK IOAPIC
Bit 0
FS0
FS1
MHz
MHz
100.0
100.0
133.32
100.0
100.0
100.0
133.32
133.32
MHz
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
66.66
100.0
133.32
133.32
66.66
0
Bit 0
Note 1
100.0
133.32
133.32
Note 1: For system operation, the BSEL lines of the CPU will program FS0, FS2 for the appropriate CPU speed, always
with SDRAM = 100MHz. After BIOS verifies the SDRAM is PC133 speed, then bit 0 can be written from the
default 0 to 1 to change the SDRAM output frequency from 100MHz to 133MHz. This will only change if the CPU
is at the 133MHz FSB speed as shown in this table. The CPU, 3v66, PCI, and IOAPIC clocks will be glitch free
during this transition, and only SDRAM will change.
Note 2: "ICS RESERVED BITS" must be writtern as "O".
Note3: Undefined bits can be written either as "1 or 0"
IDTTM Frequency Generator and Integrated Buffers for Celeron & PII/IIITM
0395F—01/25/10
5
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
