ICS9250-27
Frequency Generator and Integrated Buffers for Celeron & PII/III
TM
Truth Table
FS2
X
X
0
0
1
1
FS1 FS0
0
0
1
1
1
1
0
1
0
1
0
1
CPU
Tristate
TCLK/2
66.6 MHz
100 MHz
133 MHz
133 MHz
SDRAM
Tristate
TCLK/2
100 MHz
100 MHz
133 MHz
100 MHz
3V66
Tristate
TCLK/3
66.6
MHz
66.6
MHz
66.6
MHz
66.6
MHz
PCI
Tristate
TCLK/6
33.3 MHz
33.3 MHz
33.3 MHz
33.3 MHz
48MHz
Tristate
TCLK/2
48 MHz
48 MHz
48 MHz
48 MHz
REF
Tristate
TCLK
14.318
MHz
14.318
MHz
14.318
MHz
14.318
MHz
IOAPIC
Tristate
TCLK/6
33.3
MHz
33.3
MHz
33.3
MHz
33.3
MHz
Byte 0: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
26
25
49
Name
Reserved ID
Reserved ID
Reserved ID
Reserved ID
SpreadSpectrum
(1=On/0=Off)
48MHz 1
48MHz 0
CPUCLK2
PWD
0
0
0
0
1
1
1
1
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Note: Reserved ID bits must be wirtten as "0".
Byte 1: Control Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin#
36
37
39
40
42
43
45
46
Name
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
PWD
1
1
1
1
1
1
1
1
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
IDT
TM
Frequency Generator and Integrated Buffers for Celeron & PII/III
TM
0395F—01/25/10
4
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
