ICS9250-27
Frequency Generator and Integrated Buffers for Celeron & PII/IIITM
Byte 4: Reserved Register
(1 = enable, 0 = disable)
Bit
Pin#
Name
Reserved
PWD
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 5: Reserved Register
(1 = enable, 0 = disable)
Bit
Pin#
Name
Reserved
PWD
Description
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation.
2. PWD = Power on Default
Group Timing Relationship Table1
Group
CPU 66MHz
SDRAM 100MHz
CPU 100MHz
SDRAM 100MHz
CPU 133MHz
SDRAM 100MHz
CPU 133MHz
SDRAM 133MHz
Offset
2.5ns
7.5ns
0.0ns
Tolerance
500ps
Offset
5.0ns
5.0ns
0.0ns
Tolerance
500ps
Offset
0.0ns
0.0ns
0.0ns
Tolerance
500ps
Offset
3.75ns
0.0ns
Tolerance
500ps
CPU to SDRAM
CPU to 3V66
500ps
500ps
500ps
500ps
SDRAM to 3V66
500ps
500ps
500ps
3.75ns
500ps
3V66 to PCI
IOAPIC to PCI
USB & DOT
1.5-3.5ns
0.0ns
N/A
1.0ns
N/A
1.5-3.5ns
0.0ns
N/A
1.0ns
N/A
1.5-3.5ns
0.0ns
N/A
1.0ns
N/A
1.5 -3.5ns
0.0ns
N/A
1.0ns
N/A
Asynch
Asynch
Asynch
Asynch
IDTTM Frequency Generator and Integrated Buffers for Celeron & PII/IIITM
0395F—01/25/10
6
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
