1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Slave Mode
Slave mode allows the user much greater control of
the sensor. The interface signals utilized in slave mode
are depicted in Figure 11. The user can start and stop
integration through the use of PG_N and TX_N,
respectively. The use of the RESMEM signal to reset
pixel memories prior to ending exposure (TX_N) is
optional. The readout process is controlled by user-
supplied row control signals (ROW_STRT and
LD_SHFT_N). Additionally, the FRAME_SYNC _N sig-
nal may be used for frame synchronization.
The column counter selects the column output
SRAM cells for off-chip readout at the speed of
SYSCLK. LD_SHFT_N enables the column counter
when LOW. Data is output 3.5 clocks after LD_SHFT_N
goes LOW. The column counter is zeroed when
LD_SHFT_N is HIGH; if LD_SHFT is not high the
counter will continue.
The row counter and column counter may be
zeroed using the CLEAR signal, which is driven by reg-
ister 14. The user can set the CLEAR signal by writing
to this register through the two-wire serial interface or
by pulling down the FRAME_SYNC_N signal for two
clock cycles.
When operating in slave mode, the user should keep
in mind that both the row and column counters count
between the START and STOP values, which are set in
registers 1–4 via the two-wire serial interface. Suffi-
cient time should be allocated to allow the counters to
complete. It must also be emphasized that the row
sequencer always requires 671 clock cycles indepen-
dent of the START and STOP values (i.e., window size).
Horizontal blanking may be achieved between rows by
holding LD_SHFT_N HIGH and delaying the applica-
tion of the ROW_STRT rising edge.
Additionally, it is possible to operate the sensor in a
pipelined manner or non-pipelined manner in slave
mode (master mode is always pipelined). Pipelined
operation means that a row of data is read out of the
sensor at the same time that a new row is converted.
This is accomplished through the dual SRAM banks
that store one row for readout in one bank while the
other bank is being filled with a newly converted row.
As mentioned above, the ROW_STRT triggers the row
conversion and LD_SHFT_N enables the data output.
These can be applied nearly simultaneously to achieve
pipelined operation or applied sequentially, offset by
the row processing time, for non-pipelined operation.
NOTE:
To reduce horizontal temporal noise in slave
mode, delay readout by 80 SYSCLK.
Figure 11: Slave Mode Interface
Signals
PG_N
TX_N
SYSCLK
FRAME_SYNC_N
CONTROLLER
ROW_STRT
LD_SHFT_N
DATA
LRST_N
MT9V4O3
sensor for slave mode operation, where the sensor's
digital block requires external synchronization inputs
to trigger generation of the row conversion and read-
out sequence. The internal structure of the digital
block in slave mode includes row counter, column
counter, and row sequencer. The rising edge of the
ROW_STRT signal increments the row counter to the
next value and triggers the row sequencer. The row
sequence duration is always equal to 671 clocks, which
is fixed by the column parallel architecture. The dura-
tion of the ROW_STRT signal should be one clock
cycle.
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
MICRON [ MICRON TECHNOLOGY ]
