1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Pixel Data Format
The pixel array descriptions and details are shown
below.
signals utilized in master mode are depicted in
period is determined internal to the MT9V403.
Figure 2: Pixel Array Description
(502, 667)
8
Figure 4: Master Mode Interface
Signals
EXPOSE
SYSCLK
Dark and Isolation
Pixels
Active Pixel Array
FRAME_VALID
494
CONTROLLER
ROW_VALID
DATA
MT9V4O3
(1, 1)
LRST_N
8
659
Figure 3: Pixel Color Pattern Detail
(Bottom Left Corner)
black pixels
G
B
G
B
G
B
G
R
G
R
G
R
G
R
G
B
G
B
G
B
G
R
G
R
G
R
G
R
G
B
G
B
G
B
G
R
G
R
G
R
G
R
G
B
G
B
G
B
G
Output Format and Timing
The sensor can operate in three interface modes:
master, snapshot, or slave mode. Additionally, master
mode can be setup to allow simultaneous integration
and readout (simultaneous master mode) or sequen-
tial integration and readout (sequential master mode).
Mode selection is done via the two-wire serial inter-
face, taking less than one frame time to switch
between modes.
The default register settings program the imager to
read out the visible pixels. Therefore, the start row is 1,
start column is 9, end row is 480 and the end column is
648.
Master Mode
In master mode the sensor internally generates the
timing to initiate exposure and readout. The interface
The integration time is pre-programmed via the
two-wire serial interface and indicated by the EXPOSE
signal going HIGH. When the sensor commences, the
readout process the FRAME_VALID, ROW_VALID, and
DATA signals are output, as shown in Figure 5 on
The master mode row synchronization waveform
relationships are as shown in Figure 5 on page 5. The
FRAME_VALID signal goes HIGH, indicating the start
of frame, and 2.5 clock cycles later the ROW_VALID
signal goes HIGH, indicating the start of the first row.
The first data bit is valid on the first falling edge of
SYSCLK after ROW_VALID goes HIGH. The remaining
665 pixels for the row are valid on the subsequent fall-
ing edges of SYSCLK, after which ROW_VALID returns
to the LOW state. (Please note that in master mode 648
pixels are readout for each row.) The ROW_VALID will
then be an active HIGH envelope for subsequent rows
and the FRAME_VALID signal will be an active HIGH
envelope for subsequent frames. The time required for
one complete row operation is 671 clock cycles: 1 clock
cycle delay + 666 columns + 4 clock cycles when
ROW_VALID is LOW. With a SYSCLK of 66 MHz, this
translates into a row time of 10.2µs and a frame time of
5.1ms for full resolution (502 rows). This assumes there
is no vertical blanking or horizontal blanking and that
the exposure time is less than 5.1ms. If exposure time
becomes greater than 5.1ms, the frame time then
becomes the inverse of the exposure time (1/[exposure
time]).
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
MICRON [ MICRON TECHNOLOGY ]
