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MT9V403C12STM 参数 Datasheet PDF下载

MT9V403C12STM图片预览
型号: MT9V403C12STM
PDF下载: 下载PDF文件 查看货源
内容描述: 1月2日英寸CMOS ACTIVEPIXEL CMOS图像传感器 [1/2-INCH CMOS ACTIVEPIXEL CMOS IMAGE SENSOR]
分类和应用: 传感器图像传感器
文件页数/大小: 33 页 / 416 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 5: Master Mode Row Timing Diagram
1
12
652
653
671
671
+
169
1
12
SYSCLK
(input)
ROW _VALID
(output)
DATA [9:0]
(output)
((
))
((
))
((
))
((
))
Horizontal Blanking
((
))
XXX
9
10
((
))
((
))
648
649
XXX
((
))
((
))
9
10
NOTE:
Horizontal blanking is nominally 35 rows, and may be increased using register 5.
In master mode the frame rate is controlled by
inserting vertical and/or horizontal blanking periods
during readout, or by changing the input master clock
(SYSCLK) frequency (i.e., slowing the sensor down), or
by changing the number of rows being readout (i.e.,
window size). Table 2 shows some examples of how the
frame rate changes with window resolution and clock
speed.
Table 2:
Frame Rate vs. Resolution and Clock Speed
CLOCK SPEED (SYSCLK)
66 MHz
66 MHz
66 MHz
66 MHz
24 MHz
24MHz
24 MHz
24 MHz
10 MHz
FRAME RATE (FRAMES/SECOND)
196
392
784
1568
70
140
280
560
30
No blanking, exposure < readout
RESOLUTION (# ROWS)
502 (full resolution)
251
125
63
502 (full resolution)
251
125
63
502 (full resolution)
When horizontal blanking is utilized, the
ROW_VALID stays LOW for an additional user-pro-
grammable number of clock cycles after each row
readout. As a result the row time becomes:
RT = (1 + 66 6+ 4 + HB) x (1/fsysclk)
where HB is the horizontal blanking in SYSCLK
cycles (255 clock maximum) specified in register 5.
When vertical blanking is utilized, the FRAME_
VALID signal stays LOW for an additional user pro-
grammable number of rows after the frame is readout
(if exposure time < readout time) or exposed (if expo-
sure time > readout time). Table 3 on page 6 shows the
various scenarios for calculating the frame time, where
VB is the vertical blanking in rows (255 rows maxi-
mum) specified in register 6. The default vertical
blanking is one SYSCLK cycle, so the true vertical
blanking time is the number of blanking rows pro-
grammed plus one clock cycle.
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.