MU9C8328 Ethernet Interface
GENERAL DESCRIPTION Continued
selected, notifies the controller whether to copy or purge
the frame. The SA is then sent to the LANCAM for
comparison, and if no match is found, can be learned
to the Next Free address in the LANCAM. Scheduling
is done within the MU9C8328 so that each filtering
action completes in the time of a minimum length
frame. The filtering and learning routines are
preprogrammed in the MU9C8328, with decision
options set in the control register. A Status register is
provided so the host processor can determine the results
of activities. The specific Op-Code for the LANCAM
learning instruction is by default a MOV NF, CR, V, but it
can be overridden by writing a value to the Op-Code
register. Aging and purging activity is directly controlled
by the host processor. The READY signal notifies the host
processor that processor operations are complete. The /
INT signal notifies the processor that a network frame
has been processed and the result stored in the Status
register. The processor can turn off the network filtering
activity to have total control of the LANCAM; during this
time the controller can be notified to accept or reject
all frames.
PIN DESCRIPTIONS
All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash (“/”) are active
LOW. Inputs should never be left floating. Refer to the Electrical Characteristics section for more information.
NETWORK INTERFACE
PROCESSOR INTERFACE
SERCLK (Serial Clock, Input, TTL)
SYSCLK (System Clock, Input, TTL)
SERCLK is the nominally 10 MHz clock from the Ethernet
controller chip to the MU9C8328. Frame parsing begins
only after the internal clock detector determines that
SERCLK is valid. Internally pulled down with nominal
50K resistor.
SYSCLK is a 20 MHz to 33 MHz continuous
clock provided by the host system and is the master clock
within the MU9C8328. It is used to determine the presence
of a valid clock on the SERCLK input, operate the three
internal state machines, and provide the proper timing of
the signals on the LANCAM port. If SYSCLK is below
30 MHz, a LANCAM speed grade of 120 ns is acceptable.
Above 30 MHz, a LANCAM speed grade of 90 ns or better
is required.
SERDAT (Serial Data, Input, TTL)
SERDAT is the NRZ data from the 10 MHz Ethernet
controller chip. The MU9C8328 uses SERCLK to strobe
SERDAT looking for a Start Frame delimiter (SFD), at
which point it begins filtering and learning activity on
the Destination Address (DA) and Source Address (SA).
/CS (Chip Select, Input, TTL)
/CS is taken LOW by the host processor to gain access to
the registers of the MU9C8328 or to directly access the
LANCAM through the MU9C8328 internal
LANCAM registers. The state of /CS becomes effective
on the rising edge of SYSCLK. When /CS goes HIGH,
the MU9C8328 continues filtering and learning based on
conditions set in the Filter Control register and the frame
activity on the network interface.
/REJECT (Reject, Output, TTL)
The MU9C8328 takes /REJECT LOW to notify the
Ethernet controller chip to reject a frame under conditions
set in the Filter Control register.
/NETRDY (Network Ready, Input, TTL)
If /NETRDY is LOW, the MU9C8328 begins parsing
frame data received on the SERDAT input if SERCLK is
valid. The Ethernet controller chip, or the user, takes
/NETRDY HIGH to indicate that SERCLK or SERDAT
is invalid or is transmitting. The MU9C8328 frame parser
and internal state machines are returned to an idle state
after safely completing any LANCAM activity, while
ignoring any compare results. Internally pulled down with
nominal 50K resistor.
/AS (Address Strobe, Input, TTL)
The falling edge of /AS latches the A(2–0) bus, and when
both /AS and /CS are LOW, the processor state machine
is enabled by first rising edge of the SYSCLK to begin
writes into or reads out of the MU9C8328.
Rev. 4a
2
MUSIC [ MUSIC SEMICONDUCTORS ]
