MU9C8328 Ethernet Interface
PIN DESCRIPTIONS
Continued
/WE (Write Enable, Input, TTL)
/WE determines the direction of data flow into or out of
the MU9C8328’s processor interface. It also determines
the state of /W to the LANCAM when the processor is
accessing the MU9C8328’s internal LANCAM registers.
If /WE is LOW, the data is written into the register selected
by the A(2–0) bus. If /WE is HIGH, then data is read
out of the register selected by the A(2–0) bus.
A(2–0) (Address Bus, Input, TTL)
A(2–0) select the internal register in the MU9C8328
accessed by the host processor as shown in Table 1.
A(2–0) are latched by the falling edge of /AS.
D(15–0) (Data Bus, I/O, Three-state TTL)
D(15–0) is the processor data bus into and out of the
MU9C8328, and is demuxed to the internal registers as
selected by the A(2–0) bus. If the register selected is the
Control, Status or Op-Code register, when /WE is LOW,
D(15–0) is loaded on the second rising edge of SYSCLK
after both /AS and /CS are LOW. When /WE is HIGH,
data from the selected register is output to the D(15–0)
D Q1 5
D Q1 3
D Q1 2
D Q1 4
D Q1 1
D Q1 0
GN D
VCC
GN D
VCC
D Q9
D Q8
bus on the second rising edge of SYSLCK after both /AS
and /CS are LOW. For CAM access, the write or read
operation is completed when READY returns HIGH. If
/CS is HIGH, or if data is not being read out of the
MU9C8328, the output buffers go to HIGH-Z. Internally
pulled down with nominal 50K resistor.
READY (Ready, Output, Three-state, TTL)
When writing to the Control, Status, or Op-Code register,
READY goes LOW on the first rising edge of SYSCLK
after both /AS and /CS are LOW and returns HIGH on the
next rising edge of SYSCLK. For a read cycle from those
registers, READY may only show a negative-going spike
at the first rising edge of SYSCLK after both /AS and /CS
are LOW. The data will be valid before the next rising
edge of SYSCLK. When writing or reading to/from the
CAM registers, READY will go LOW on the first rising
edge of SYSCLK after both /CS and /AS are LOW.
READY returns HIGH four SYSCLK cycles later,
indicating that the CAM write cycle will complete after
the next rising edge of SYSCLK.
VCC
D Q6
80
75
70
65
60
D Q3
79
78
77
76
74
73
72
71
69
68
67
66
64
63
62
61
59
58
57
56
55
54
53
52
GN D
51
D Q7
D Q5
D Q4
D Q2
D Q1
D Q0
81
82
83
/FF
/M F
/E C
/C M
/E
/W
84
85
86
87
88
89
90
GN D
VCC
91
92
93
94
/R E S E T
RE ADY
/IN T
/W E
/A S
/C S
95
96
97
98
99
1 00
50
49
48
47
46
45
44
43
42
S E R C LK
S E RDAT
/R E J E C T
N TE S T OU T
N TE S T_ E N
GN D
VCC
MU9C8328-RDC
100-pin PQFP
(Top View)
41
40
39
38
37
36
35
34
33
32
31
/N E TR D Y
D0
17
14
19
20
21
22
23
24
25
26
27
28
10
11
12
13
15
16
18
29
VCC
D15
A1
A0
D13
A2
D12
D11
D14
D10
D9
D8
D7
D6
D5
D4
D3
D2
S Y S C LK
GN D
GN D
VCC
PINOUT DIAGRAM
3
Rev. 4a
GN D
VCC
D1
30
2
3
4
5
6
7
1
8
9
MUSIC [ MUSIC SEMICONDUCTORS ]
