PE3339
Advance Information
Figure 2. Pin Configuration
V
DD
Enh
S_WR
Sdata
Sclk
GND
FSELS
E_WR
V
DD
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
f
r
GND
N/C
CP
V
DD
Dout
LD
Cext
GND
F
in
F
in
10
Table 1. Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
V
DD
Enh
S_WR
Sdata
Sclk
GND
FSELS
E_WR
V
DD
F
in
F
in
GND
Cext
LD
Dout
V
DD
Type
(Note 1)
Input
Input
Input
Input
Description
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing required.
Enhancement mode. When asserted low (“0”), enhancement register bits are functional. Internal 70 k
Ω
pull-up
resistor.
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked. Primary register data are
transferred to the secondary register on S_WR rising edge.
Binary serial data input. Input data entered MSB first.
Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR “low”) or the 8-bit
enhancement register (E_WR “high”) on the rising edge of Sclk.
Ground.
Input
Input
(Note 1)
Input
Input
Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for programming of internal
counters. Internal 70 k
Ω
pull-down resistor.
Enhancement register write enable. While E_WR is “high”, Sdata can be serially clocked into the enhancement
register on the rising edge of Sclk. Internal 70 k
Ω
pull-down resistor.
Same as pin 1.
Prescaler input from the VCO. Max frequency input is 3.0 GHz.
Prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be
connected in series with a 50
Ω
resistor to the ground plane.
Ground.
Output
Output,
OD
Output
(Note 1)
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 k
Ω
series resistor. Connecting Cext to an
external capacitor will low pass filter the input to the inverting amplifier used for driving LD.
Lock detect is an open drain logical inversion of CEXT. When the loop is in lock, LD is high impedance,
otherwise LD is a logic low (“0”).
Data out function, Dout, enabled in enhancement mode.
Same as pin 1.
File No. 70/0048~02A
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Copyright
©
Peregrine Semiconductor Corp. 2004
UTSi
®
CMOS RFIC SOLUTIONS
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