PE3339
Advance Information
Table 6. AC Characteristics
V
DD
= 3.0 V, -40° C < T
A
< 85° C, unless otherwise specified
Symbol
f
Clk
t
ClkH
t
ClkL
t
DSU
t
DHLD
t
PW
t
CWR
t
CE
t
WRC
t
EC
F
in
P
Fin
F
in
P
Fin
Reference Divider
f
r
P
fr
Phase Detector
f
c
Comparison frequency
(Note 3)
20
MHz
SSB Phase Noise (F
in
= 1.3 GHz, f
r
= 10 MHz, f
c
= 1.25 MHz, LBW = 70 kHz, V
DD
= 3.0 V, Temp = -40
°
C
)
100 Hz Offset
1 kHz Offset
Note 1:
Parameter
Serial data clock frequency
Serial clock HIGH time
Serial clock LOW time
Sdata set-up time to Sclk rising edge
Sdata hold time after Sclk rising edge
S_WR pulse width
Sclk rising edge to S_WR rising edge
Sclk falling edge to E_WR transition
S_WR falling edge to Sclk rising edge
E_WR transition to Sclk rising edge
Operating frequency
Input level range
Operating frequency
Input level range
Operating frequency
Reference input power (Note 2)
Conditions
(Note 1)
Min
Max
10
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Control Interface and Latches (see Figures 3, 4, 5)
30
30
10
10
30
30
30
30
30
500
External AC coupling
-5
50
External AC coupling
(Note 3)
Single ended input
-2
-5
3000
5
300
5
100
Main Divider (Including Prescaler)
MHz
dBm
MHz
dBm
MHz
dBm
Main Divider (Prescaler Bypassed)
-75
-85
dBc/Hz
dBc/Hz
fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk
specification.
CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p. For optimum phase
noise performance, the reference input falling edge rate should be faster than 80mV/ns.
Parameter is guaranteed through characterization only and is not tested.
Note 2:
Note 3:
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©
Peregrine Semiconductor Corp. 2004
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