ASM5P23S08AF-3-16-TR 参数 Datasheet PDF下载

November 2006

rev 1.5

Block Diagram

FBK

PLL

MUX

ASM5P23S08A

/2

REF

/2

CLKA1

Extra Divider (-5H)

Extra Divider (-3, -4)

CLKA2

CLKA3

CLKA4

S2

Select Input

Decoding

S1

/2

CLKB1

Extra Divider (-2, -3)

CLKB2

CLKB3

CLKB4

ASM5P23S08A

Select Input Decoding for ASM5P23S08A

S2

0

0

1

1

S1

0

1

0

1

Clock A1 - A4

Three-state

Driven

Driven

1

Driven

Clock B1 - B4

Three-state

Three-state

Driven

Driven

Output Source

PLL

PLL

Reference

PLL

PLL Shut-Down

Y

N

Y

N

ASM5P23S08A Configurations

Device

ASM5P23S08A-1

ASM5P23S08A-1H

ASM5P23S08A-2

ASM5P23S08A-2

ASM5P23S08A-3

ASM5P23S08A-3

ASM5P23S08A-4

ASM5P23S08A-5H

Feedback From

Bank A or Bank B

Bank A or Bank B

Bank A

Bank B

Bank A

Bank B

Bank A or Bank B

Bank A or Bank B

Bank A Frequency

Reference

Reference

Reference

2 X Reference

2 X Reference

4 X Reference

2 X Reference

Reference /2

Bank B Frequency

Reference

Reference

Reference /2

Reference

Reference or Reference

2

2 X Reference

2 X Reference

Reference /2

Note:

1. Outputs are non- inverted on 23S08A-2 and 23S08A-3 in bypass mode, S2 = 1 and S1 = 0.

2. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the ASM5P23S08A-2.

3.3V ‘SpreadTrak’ Zero Delay Buffer

Notice: The information in this document is subject to change without notice.

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