November 2006
rev 1.5
Pin Configuration
REF
CLKA1
CLKA2
V
DD
GND
CLKB1
CLKB2
S2
1
2
3
4
5
6
7
8
16
15
14
FBK
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
ASM5P23S08A
ASM5P2308A
13
12
11
10
9
Pin Description for ASM5P23S08A
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
REF
3
CLKA1
4
CLKA2
4
V
DD
GND
CLKB1
4
CLKB2
4
S2
5
S1
5
CLKB3
4
CLKB4
4
GND
V
DD
CLKA3
4
CLKA4
4
FBK
Description
Input reference frequency, 5V tolerant input
Buffered clock output, bank A
Buffered clock output, bank A
3.3V supply
Ground
Buffered clock output, bank B
Buffered clock output, bank B
Select input, bit 2
Select input, bit 1
Buffered clock output, bank B
Buffered clock output, bank B
Ground
3.3V supply
Buffered clock output, bank A
Buffered clock output, bank A
PLL feedback input
Notes:
3. Weak pull-down.
4. Weak pull-down on all outputs.
5. Weak pull-up on these inputs.
3.3V ‘SpreadTrak’ Zero Delay Buffer
Notice: The information in this document is subject to change without notice.
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PULSECORE [ PulseCore Semiconductor ]
