CY2277A
Pin Summary
Name
V
DDQ3
V
DDQ2
V
DDCPU
AV
DD
V
SS
XTALIN
[1]
XTALOUT
[1]
MODE
SEL
SDATA
SCLK
PWR_DWN
PWR_SEL
SDRAM7/PCI_STOP
SDRAM6/CPU_STOP
SDRAM[0:5]
CPUCLK[0:3]
PCICLK[0:5]
PCICLK_F
IOAPIC
REF[0:1]
USBCLK/IOCLK
Pins
7, 15, 21, 28, 34
46
40
25, 48
4
5
6
18
19
20
44
47
26
27
36, 35, 33, 32, 30, 29
42, 41, 39, 38
9, 11, 12, 13, 14, 16
8
45
1, 2
22, 23
Description
3.3V Digital voltage supply
IOAPIC Digital voltage supply, 2.5V
CPU Digital voltage supply, 2.5V or 3.3V
3.3V Analog voltage supply
Reference crystal input
Reference crystal feedback
Mode select input, enables power management features
Select input to enable 66.66 MHz or 60 MHz CPU clock (See Function
tables.)
SMBus serial data input for serial configuration port
SMBus serial clock input for serial configuration port
Active low control input to put osc., PLLs, and outputs in power down state
Power select input, indicates whether V
DDCPU
is at 2.5V or 3.3V
HIGH = 3.3V, LOW=2.5V (internal pull-up to V
DD
)
SDRAM clock output. Also, active LOW control input to stop PCI clocks,
enabled when MODE is LOW
SDRAM clock output. Also, active LOW control input to stop CPU clocks,
enabled when MODE is LOW
SDRAM clock outputs, have same frequency as CPU clocks
CPU clock outputs
PCI clock outputs
PCI clock output, free-running
IOAPIC clock output
Reference clock outputs, 14.318 MHz. REF0 drives 45 pF load
USB or IO clock outputs, frequency selected by serial word
3, 10, 17, 24, 31, 37, 43 Ground
Note:
1. For best accuracy, use a parallel-resonant crystal, C
LOAD
= 18 pF.
Table 1.
CY2277A Selector Guide
Clock Outputs
-1/-1M
4
--
--
7
[2]
6/8
2
1
2
1–6 ns
-3
--
4
--
7
[2]
6/8
2
1
2
1–6 ns
-7M
4
--
--
7
[2]
6/8
2
1
2
<1 ns
-12/-12M/-12I
4
--
--
7
[2]
6/8
2
1
2
1–4 ns
CPU (60, 66.6 MHz)
CPU (33.3, 66.6 MHz)
CPU (SMBus selectable)
PCI (CPU/2)
SDRAM
USB/IO (48 or 24 MHz)
IOAPIC (14.318 MHz)
Ref (14.318 MHz)
CPU-PCI delay
Note:
2. One free-running PCI clock
Rev 1.0, November 25, 2006
Page 2 of 18
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