CY2277A
Function Table (-3)
SEL
0
1
XTALIN
14.318 MHz
14.318 MHz
CPUCLK[0:3]
SDRAM[0:7]
33.33 MHz
66.67 MHz
PCICLK[0:5]
PCICLK_F
16.67 MHz
33.33 MHz
REF[0:1]
IOAPIC
14.318 MHz
14.318 MHz
USBCLK / IOCLK
[3]
48.0 MHz / 24.0 MHz
48.0 MHz / 24.0 MHz
Function Table (-1, -1M, -7M, -12, -12M, -12I)
SEL
0
1
XTALIN
14.318 MHz
14.318 MHz
CPUCLK[0:3]
SDRAM[0:7]
60.0 MHz
66.67 MHz
PCICLK[0:5]
PCICLK_F
30.0 MHz
33.33 MHz
REF[0:1]
IOAPIC
14.318 MHz
14.318 MHz
USBCLK / IOCLK
[3]
48.0 MHz / 24.0 MHz
48.0 MHz / 24.0 MHz
Actual Clock Frequency Values (-1, -1M, -3, -7M, -12, -12M, -12I)
Clock Output
CPUCLK, SDRAM
CPUCLK, SDRAM
USBCLK
[4]
IOCLK
Target
Frequency (MHz)
66.67
60.0
48.0
24.0
Actual
Frequency (MHz)
66.654
60.0
48.008
24.004
–195
0
167
167
• Output impedance: 25
(typical) measured at 1.5V
PPM
CPU and PCI Clock Driver Strengths
• Matched impedances on both rising and falling edges on
the output drivers
Power Management Logic
CPU_STOP
X
0
0
1
1
PCI_STOP
X
0
1
0
1
PWR_DWN
0
1
1
1
1
CPUCLK
LOW
LOW
LOW
66/60 MHz
66/60 MHz
PCICLK
LOW
LOW
33/30 MHz
LOW
33/30 MHz
PCICLK_F
Stopped
Running
Running
Running
Running
Other Clocks
Stopped
Running
Running
Running
Running
Osc.
Off
Running
Running
Running
Running
PLLs
Off
Running
Running
Running
Running
Select Functions
Outputs
Functional Description
Three-State
Test Mode
Hi-Z
TCLK/2
[5]
CPU
PCI, PCI_F
Hi-Z
TCLK/4
SDRAM
Hi-Z
TCLK/2
Ref
Hi-Z
TCLK
IOAPIC
Hi-Z
TCLK
IOCLK
Hi-Z
TCLK/4
USBCLK
Hi-Z
TCLK/2
Notes:
3. On power-up, the default frequency on these outputs is 48 MHz.
4. Meets Intel USB clock requirements.
5. TCLK supplied on the XTALIN, PIN 4.
Rev 1.0, November 25, 2006
Page 3 of 18
SPECTRALINEAR [ SPECTRALINEAR INC ]
