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CY2277APAC-12M 参数 Datasheet PDF下载

CY2277APAC-12M图片预览
型号: CY2277APAC-12M
PDF下载: 下载PDF文件 查看货源
内容描述: Pentium㈢ / II , 6X86 , K6时钟合成器/驱动器,用于桌面/移动PC与Intel㈢ 82430TX和2个DIMM或3 SO- DIMM内存模块 [Pentium㈢/II, 6x86, K6 Clock Synthesizer/Driver for Desktop/ Mobile PCs with Intel㈢ 82430TX and 2 DIMMs or 3 SO-DIMMs]
分类和应用: 驱动器PC时钟
文件页数/大小: 18 页 / 293 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY2277A
Serial Configuration Map
• The Serial bits will be read by the clock driver in the following order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
• Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
• Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
• Reserved and unused bits should be programmed to “0”.
• SMBus Address for the CY2277A is:
Table 2.
A6
1
A5
1
A4
0
A3
1
A2
0
A1
0
A0
1
R/W
----
Byte 0: Functional and Frequency Select Clock
Register (1 = Enable, 0 = Disable)
Bit
Pin #
Description
(Reserved) drive to ‘0’
(Reserved) drive to ‘0’ on -1, -1M, -3, -7M,
-12, -12M, -12I
(Reserved) drive to ‘0’ on -1, -1M, -3, -7M,
-12, -12M, -12I
(Reserved) drive to ‘0’ on -1, -1M, -3, -7M,
-12, -12M, -12I
Bit 7 --
Bit 6 --
Bit 5 --
Bit 4 --
Byte 0: Functional and Frequency Select Clock
Register (1 = Enable, 0 = Disable)
Bit 3 23
Bit 2 22
Bit 1 --
Bit 0
48/24 MHz (Frequency Select) 1 = 48 MHz
(default), 0 = 24 MHz
48/24 MHz (Frequency Select) 1 = 48 MHz
(default), 0 = 24 MHz
Bit 1
1
1
0
0
Bit 0
1 - Three-State (see table below)
0 - N/A
1 - Test Mode (see table below)
0 - Normal Operation
Rev 1.0, November 25, 2006
Page 4 of 18