8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
The SST39VF800Q/VF800 also have the Auto Low
Powermodewhichputsthedeviceinanearstandbymode
after data has been accessed with a valid read operation.
This reduces the IDD active read current from typically 15
mA to typically 3 µA. The Auto Low Power mode reduces
thetypicalIDD activereadcurrenttotherangeof1mA/MHz
of read cycle time. The device exits the Auto Low Power
mode with any address transition or control signal transi-
tionusedtoinitiateanotherreadcycle,withnoaccesstime
penalty.
byte command sequence with Block Erase command
(50H) and block address (BA) in the last bus cycle. The
address lines A15-A18 are used to determine the block
address. The sector or block address is latched on the
falling edge of the sixth WE# pulse, while the command
(30Hor50H)islatchedontherisingedgeofthesixthWE#
pulse. The internal Erase operation begins after the sixth
WE#pulse.TheendofEraseoperationcanbedetermined
using either Data# Polling or Toggle Bit methods. See
Figures 9 and 10 for timing waveforms. Any commands
issued during the Sector or Block Erase operation are
ignored.
Read
The Read operation of the SST39VF800Q/VF800 is con-
trolledbyCE#andOE#,bothhavetobelowforthesystem
to obtain data from the outputs. CE# is used for device
selection. When CE# is high, the chip is deselected and
onlystandbypowerisconsumed.OE#istheoutputcontrol
andisusedtogatedatafromthe outputpins.Thedatabus
isinhighimpedancestatewheneitherCE#orOE#ishigh.
Refer to the Read cycle timing diagram for further details
(Figure 3).
Chip Erase Operation
The SST39VF800Q/VF800 provide a Chip Erase opera-
tion,whichallowstheusertoerasetheentirememoryarray
to the “1” state. This is useful when the entire device must
be quickly erased.
The Chip Erase operation is initiated by executing a six-
byte command sequence with Chip Erase command
(10H) at address 5555H in the last byte sequence. The
Erase operation begins with the rising edge of the sixth
WE# or CE#, whichever occurs first. During the Erase
operation,theonlyvalidreadisToggleBitorData#Polling.
SeeTable4forthecommandsequence,Figure8fortiming
diagram, and Figure 19 for the flowchart. Any commands
issued during the Chip Erase operation are ignored.
Word Program Operation
The SST39VF800Q/VF800 are programmed on a word-
by-word basis. The Program operation consists of three
steps. The first step is the three-byte load sequence for
SoftwareDataProtection. Thesecondstepistoloadword
address and word data. During the Word Program opera-
tion,theaddressesarelatchedonthefallingedgeofeither
CE#orWE#,whicheveroccurslast.Thedataislatchedon
the rising edge of either CE# or WE#, whichever occurs
first.ThethirdstepistheinternalProgramoperationwhich
is initiated after the rising edge of the fourth WE# or CE#,
whichever occurs first. The Program operation, once initi-
ated, will be completed within 20 µs. See Figures 4 and 5
for WE# and CE# controlled Program operation timing
diagrams and Figure 16 for flowcharts. During the Pro-
gramoperation, theonlyvalidreadsareData#Pollingand
ToggleBit.DuringtheinternalProgramoperation,thehost
is free to perform additional tasks. Any commands issued
during the internal Program operation are ignored.
Write Operation Status Detection
The SST39VF800Q/VF800 provide two software means
to detect the completion of a write (Program or Erase)
cycle, inordertooptimizethesystemwritecycletime. The
software detection includes two status bits: Data# Polling
(DQ7) and Toggle Bit (DQ6). The end of write detection
mode is enabled after the rising edge of WE#, which
initiates the internal program or erase operation.
Theactualcompletionofthenonvolatilewriteisasynchro-
nous with the system; therefore, either a Data# Polling or
Toggle Bit read may be simultaneous with the completion
of the write cycle. If this occurs, the system may possibly
get an erroneous result, i.e., valid data may appear to
conflictwitheitherDQ7orDQ6.Inordertopreventspurious
rejection, if an erroneous result occurs, the software rou-
tineshouldincludealooptoreadtheaccessedlocationan
additional two (2) times. If both reads are valid, then the
device has completed the write cycle, otherwise the rejec-
tion is valid.
Sector/Block Erase Operation
The Sector/Block Erase operation allows the system to
erase the device on a sector-by-sector (or block-by-block)
basis. The SST39VF800Q/VF800 offer both small Sector
Erase and Block Erase mode. The sector architecture is
basedonuniformsectorsizeof2KWord.TheBlockErase
mode is based on uniform block size of 32 KWord. The
SectorEraseoperationisinitiatedbyexecutingasix-byte-
command sequence with Sector Erase command (30H)
andsectoraddress(SA)inthelastbuscycle. Theaddress
lines A11-A18 are used to determine the sector address.
The Block Erase operation is initiated by executing a six-
Data# Polling (DQ7)
When the SST39VF800Q/VF800 are in the internal Pro-
gram operation, any attempt to read DQ7 will produce the
complementofthetruedata. OncetheProgramoperation
is completed, DQ7 will produce true data. The device is
© 1999 Silicon Storage Technology, Inc.
343-04 2/99
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