8 Megabit Multi-Purpose Flash
SST39VF800Q / SST39VF800
Advance Information
then ready for the next operation. During internal Erase
operation, any attempt to read DQ7 will produce a ‘0’. Once
the internal Erase operation is completed, DQ7 will pro-
duce a ‘1’. The Data# Polling is valid after the rising edge
of fourth WE# (or CE#) pulse for Program operation. For
Sector, Block or Chip Erase, the Data# Polling is valid after
the rising edge of sixth WE# (or CE#) pulse. See Figure 6
for Data# Polling timing diagram and Figure 17 for a
flowchart.
Toggle Bit (DQ
6
)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ
6
will produce alternating 1’s
and 0’s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling. The device is then ready for the next opera-
tion. The Toggle Bit is valid after the rising edge of fourth
WE# (or CE#) pulse for Program operation. For Sector,
Block or Chip Erase, the Toggle Bit is valid after the rising
edge of sixth WE# (or CE#) pulse. See Figure 7 for Toggle
Bit timing diagram and Figure 17 for a flowchart.
Data Protection
The SST39VF800Q/VF800 provide both hardware and
software features to protect nonvolatile data from inadvert-
ent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than
5 ns will not initiate a write cycle.
V
DD
Power Up/Down Detection: The Write operation is
inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Software Data Protection (SDP)
The SST39VF800Q/VF800 provide the JEDEC approved
Software Data Protection scheme for all data alteration
operations, i.e., Program and Erase. Any Program opera-
tion requires the inclusion of the three byte sequence. The
three-byte load sequence is used to initiate the Program
operation, providing optimal protection from inadvertent
Write operations, e.g., during the system power-up or
power-down. Any Erase operation requires the inclusion of
six-byte sequence. The SST39VF800Q/VF800 devices
are shipped with the software data protection permanently
enabled. See Table 4 for the specific software command
codes. During SDP command sequence, invalid com-
mands will abort the device to read mode within T
RC
. The
contents of DQ
15
-DQ
8
are “Don’t Care” during any SDP
command sequence.
Common Flash Memory Interface (CFI)
The SST39VF800Q/VF800 also contain the CFI informa-
tion to describe the characteristics of the device. In order to
enter the CFI Query mode, the system must write three-
byte sequence, same as product ID entry command with
98H (CFI Query command) to address 5555H in the last
byte sequence. Once the device enters the CFI Query
mode, the system can read CFI data at the addresses given
in tables 5 through 7. The system must write the CFI Exit
command to return to Read mode from the CFI Query
mode.
Product Identification
The Product Identification mode identifies the devices as
the SST39VF800Q, SST39VF800 and manufacturer as
SST. This mode may be accessed by hardware or software
operations. The hardware operation is typically used by a
programmer to identify the correct algorithm for the
SST39VF800Q/VF800. Users may wish to use the Soft-
ware Product Identification operation to identify the part
(i.e., using the device code) when using multiple manufac-
turers in the same socket. For details, see Table 3 for
hardware operation or Table 4 for software operation,
Figure 11 for the Software ID Entry and Read timing
diagram and Figure 18 for the ID Entry command sequence
flowchart.
T
ABLE
1: P
RODUCT
I
DENTIFICATION
T
ABLE
Address
Manufacturer’s Code
Device Code
0000H
0001H
Data
00BFH
2781H
343 PGM T1.0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Product Identification Mode Exit/CFI Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command se-
quence, which returns the device to the Read operation.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
apparently causes the device to behave abnormally, e.g.,
not read correctly. Please note that the Software ID Exit/CFI
Exit command is ignored during an internal Program or
Erase operation. See Table 4 for software command codes,
Figure 13 for timing waveform and Figure 18 for a flowchart.
V
DDQ
- I/O Power Supply
This feature is available only on the SST39VF800Q. This
pin functions as power supply pin for input/output buffers. It
should be tied to V
DD
(2.7-3.6V) in a 3.0V-only system. It
should be tied to a 5.0V±10% (4.5-5.5V) power supply in a
mixed voltage system environment where flash memory
has to be interfaced with 5V system chips. The V
DDQ
pin is
not offered on the SST39VF800, instead it is a No Connect
pin.
3
343-04 2/99
© 1999 Silicon Storage Technology, Inc.
SST [ SILICON STORAGE TECHNOLOGY, INC ]
