4 Mbit LPC Flash
SST49LF040
Advance Information
TABLE 7: O
PERATION
M
ODES
S
ELECTION
(PP M
ODE
)
Mode
Read
Program
Erase
Reset
Write Inhibit
Product Identification
RST#
OE#
V
IL
WE#
DQ
D
OUT
D
IN
X
1
High Z
High Z/D
OUT
High Z/D
OUT
Manufacturer’s ID (BFH)
Device ID
2
Address
A
IN
A
IN
Sector or Block address,
XXH for Chip-Erase
X
X
X
See Table 8
T7.2 562
V
IH
V
IH
V
IH
V
IL
V
IH
V
IL
V
IL
X
X
V
IH
V
IH
X
V
IL
X
V
IL
V
IH
X
V
IH
V
IH
V
IH
1. X can be V
IL
or V
IH
, but no other value.
2. Device ID 51H for SST49LF040
TABLE 8: S
OFTWARE
C
OMMAND
S
EQUENCE
(A
LL
I
NTERFACES
)
Command
Sequence
Byte-
Program
Sector-
Erase
Block-Erase
Chip-Erase
6
Software
ID Entry
Software
ID Exit
8
Software
ID Exit
8
1st
1
Cycle
Addr
2
YYYY 5555H
2nd
1
Cycle
Data
AAH
3rd
1
Cycle
Data
55H
4th
1
Cycle
Data
A0H
5th
1
Cycle
Data
Data
6th
1
Cycle
Data
Addr
2
Data
Addr
2
YYYY 2AAAH
Addr
2
YYYY 5555H
Addr
2
PA
3
Addr
2
YYYY 5555H
AAH
YYYY 2AAAH
55H
YYYY 5555H
80H
YYYY 5555H
AAH
YYYY 2AAAH
55H
SAx
4
30H
YYYY 5555H
YYYY 5555H
YYYY 5555H
AAH
AAH
AAH
YYYY 2AAAH
YYYY 2AAAH
YYYY 2AAAH
55H
55H
55H
YYYY 5555H
YYYY 5555H
YYYY 5555H
80H
80H
90H
YYYY 5555H
YYYY 5555H
Read ID
7
AAH
AAH
YYYY 2AAAH
YYYY 2AAAH
55H
55H
BAx
5
YYYY 5555H
50H
10H
XXXX XXXXH
F0H
YYYY 5555H
AAH
YYYY 2AAAH
55H
YYYY 5555H
F0H
T8.3 562
1. LPC mode uses consecutive Write cycles to complete a command sequence; PP mode uses consecutive bus cycles to complete a
command sequence.
2. YYYY = A[31:16]
In LPC mode, during SDP command sequence, YYYY must be within memory address range specified in Figures 4 and 5.
In PP mode, YYYY can be V
IL
or V
IH
.
3. PA = Program Byte address
4. SAx for Sector-Erase Address
5. BAx for Block-Erase Address
6. Chip-Erase is supported in PP mode only
7. SST Manufacturer’s ID = BFH, is read with A
0
= 0.
With A
18
-A
1
= 0; 49LF040 Device ID = 51H, is read with A
0
= 1.
8. Both Software ID Exit operations are equivalent
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
16
SST [ SILICON STORAGE TECHNOLOGY, INC ]
