4 Mbit LPC Flash
SST49LF040
Advance Information
Absolute Maximum Stress Ratings
(Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this
datasheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D.C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to
V
DD
+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to
V
DD
+2.0V
Package Power Dissipation Capability (Ta=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current
1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
O
PERATING
R
ANGE
Range
Commercial
Ambient Temp
0°C to +85°C
V
DD
3.0-3.6V
AC C
ONDITIONS
OF
T
EST
Input Rise/Fall Time . . . . . . . . . . . . . . . 3 ns
Output Load . . . . . . . . . . . . . . . . . . . . . C
L
= 30 pF
See Figures 29 and 30
TABLE 9: DC O
PERATING
C
HARACTERISTICS
(A
LL
I
NTERFACE
)
Limits
Symbol Parameter
I
DD
Active V
DD
Current
Read
Write
2
I
SB
Standby V
DD
Current
(LPC Interface)
Ready Mode V
DD
Current (LPC Interface)
Input Current for IC:
ID[3:0] pins for SST49LF040
ID[3:1] pins for SST49LF080A
Input Leakage Current
Output Leakage Current
INIT# Input High Voltage
INIT# Input Low Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
0.9 V
DD
1.1
-0.5
-0.5
0.5 V
DD
12
24
100
mA
mA
µA
Min
Max
Units Test Conditions
1
Address input=V
IL
/
V
IH
, at f=1/T
RC
Min,
V
DD
=V
DD
Max
OE#=
V
IL
, WE#=
V
IH,
All I/Os open
OE#=
V
IH
, V
DD
=V
DD
Max
LFRAME#=V
IH
, f=33 MHz, CE#=V
IH
V
DD
=V
DD
Max,
All other inputs
≥
0.9 V
DD
or
≤
0.1 V
DD
LFRAME#=V
IL
, f=33 MHz, V
DD
=V
DD
Max
All other inputs
≥
0.9 V
DD
or
≤
0.1 V
DD
V
IN
=GND to V
DD
, V
DD
=V
DD
Max
I
RY3
I
I
10
200
mA
µA
I
LI
I
LO
V
IHI
V
ILI
V
IL
1
1
V
DD
+0.5
0.4
0.3 V
DD
V
DD
+0.5
0.1 V
DD
µA
µA
V
V
V
V
V
V
V
IN
=GND to V
DD
, V
DD
=V
DD
Max
V
OUT
=GND to V
DD
, V
DD
=V
DD
Max
V
DD
=V
DD
Max
V
DD
=V
DD
Max
V
DD
=V
DD
Min
V
DD
=V
DD
Max
I
OL
=1500µA, V
DD
=V
DD
Min
I
OH
=-500 µA, V
DD
=V
DD
Min
T9.1 562
V
IH
V
OL
V
OH
1. Test conditions apply to PP mode.
2. I
DD
active while Erase or Program is in progress.
3. The device is in Ready Mode when no activity is on the LPC bus.
©2001 Silicon Storage Technology, Inc.
S71213-00-000 11/01 562
17
SST [ SILICON STORAGE TECHNOLOGY, INC ]
