VIS
2.4 Operative Command Table Notes 1
Address
Current state CS RAS CAS WE
Idle
H
X
X
X X
L
H
H
X X
L
H
L
H BA, CA, A10
L
H
L
L BA, CA, A10
L
L
H
H BR, RA
L
L
H
L BA, A10
L
L
L
H X
L
L
L
L Op - Code
Row active
H
X
X
X X
L
H
H
X X
L
H
L
H BA, CA, A10
L
H
L
L BA, CA, A10
L
L
H
H BA, RA
L
L
H
L BA, A10
L
L
L
H X
L
L
L
L Op - Code
Read
H
X
X
X X
L
L
L
L
L
L
L
L
Write
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
L
H
H
L
L
H
H
L
L
X
H
H
L
L
H
H
L
L
H
L
H
L
H
L
H
L
X
H
L
H
L
H
L
H
L
X
X
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
X
Op - Code
X
X
X
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
X
Op - Code
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
(1/3)
Command
DESL
NOP or BST
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MPS
DESL
NOP or BST
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
DESL
NOP
BST
WRIT/WRITA
ACT
PRE/PALL
REF/SELF
MRS
Action
Nop or Power down
Nop or Power down
ILLEGAL
Row active
Nop
Refresh or Self refresh
Mode register access
Nop
Nop
Notes
2
2
3
3
READ/READA ILLEGAL
4
READ/READA Begin read : Determine AP
Begin write : Determine AP
ILLEGAL
Precharge
ILLEGAL
ILLEGAL
Continue burst to end
Continue burst to end
Burst stop
5
5
3
6
→
Row active
→
Row active
→
Row active
7
7,8
3
READ/READA Term burst, new read : Determine AP
Term burst, start write : Determine AP
ILLEGAL
Term burst, precharging
ILLEGAL
ILLEGAL
Continue burst to end
Continue burst to end
Burst stop
→
write recovering
→
write recovering
7,8
7
3
9
→
Row active
READ/READA Term burst, start read : Determine AP
Term burst, new write : Determine AP
ILLEGAL
Term burst, precharging
ILLEGAL
ILLEGAL
Document : 1G5-0099
Rev.1
Page 11
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
