VIS
A.C Characteristics : (Ta = 0 to 70°C V
DD
= 3.3V
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
±
0.3V, V
SS
= 0V)
-8H
Min
8
10
6
6
3
3
2
1
2
1
2
1
2
1
3
0
6
6
1
16
20
20
48
70
1
1+ t
RP
8
1
0.2
2
1
1
16
20
20
48
70
1
1+ t
RP
8
1
0.2
2
1
3
3
2
1
2
1
2
1
2
1
3
0
6
6
2
20
26
26
60
90
1
1+ t
RP
10
1
0.2
2
1
VG3664321 (4) 1 (2) B
-8L
Min
8
12
6
6
3
3
3
1
3
1
3
1
3
1
3
0
6
6
Max
Min
10
15
6
6
Unit
-10
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CLK
CLK
ns
ns
CLK
CLK
ms
Parameter
CAS
Latency symbol
3
2
3
2
t
ck3
t
ck2
t
Ac3
t
Ac2
t
CH
t
CL
t
CKS
t
CKH
t
AS
t
AH
t
CMS
t
CMH
t
DS
t
DH
t
OH
t
LZ
t
HZ
t
OHN
t
RRD
t
RCD
t
RP
t
RAS
t
RC
t
BDL
t
DAL
t
DPL
t
T(1)
t
T(2)
t
RSC
t
SRX
t
REF
Max
CLK cycle time
(1)
CLK to valid output delay
CLK high pulse width
CLK low pulse width
CKE setup time
CKE hold time
Address setup time
Address hold time
Command setup time
Command hold time
Data input setup time
Data input hold time
Output data hold time
CLK to output in low - Z
CLK to output in Hi - Z
CLK to output in Hi - Z without load
Row active to active delay
RAS to CAS delay
Row precharge time
ROW active time
ROW cycle time
Last data in to burst stop
Data - in to ACT(REF) command
Data - in to precharge
Transition time
Mode reg. set cycle
Self refresh exit time
Refresh time
3
2
120K
120K
120K
10
5
10
5
10
5
64
64
64
Notes : (1) The input clock should be stable and continuous. (jitter
≤
7% * t
CK
)
Document : 1G5-0099
Rev.1
Page 8
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
