VIS
Test Conditions for LVTTL Compatible :
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
A. C Characteristics : (Ta = 0 to 70°C V
DD
= 3.3V
±
0.3V
SS
= 0V)
Input timing reference level/
Output timing reference level
Output load condition
1.4V
50pF
AC input Levels (V
IH
/V
IL
)
Input rise and fall time
2.0/0.8V
1ns
AC Test Load Circuits (for LVTTL interface) :
1.4V
V
DDQ
V
OUT
V
DDQ
50
Ω
Z = 50
Ω
50PF
Device
Under
Test
Test Conditions for SSTL - 3 Interface
Input Hihg (min)/Input low (max) Voltage
VREF + 0.4V/ Input Reference Voltage
(VREF)
VREF - 0.4V
Timing Reference Levels of Output Signals 0.45 x VDDQ Input Signal MAX. Slew Rate
Input Signal MAX. Peak to Peak Swing
2.0V
Output Circuit
Min. Required output pull - up under AC
test load
VTT + 0.8V
Min. Required output pull -
down under AC test load
0.45 x VDDQ
1V/ns
See Figure
Below
VTT - 0.8V
AC Test Load Circuits (for SSTL - 3 interface) :
V
DDQ
V
REF
V
DDQ
0.45 * V
DDQ
V
TT
= 0.45 * V
DDQ
RT2 = 50 Ohms
V
OUT
RS = 25Ohms
Z = 50 Ohms
VIN
Device
Under
Test
RT1 = 50 Ohms
C
LOAD
= 30 pF
V
TT
= 0.45 * V
DDQ
V
SS
V
REF
= 0.45 * V
DD
Document : 1G5-0099
Rev.1
Page 7
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
