VIS
Preliminary
VG3664321(4)1(2)BT
CMOS Synchronous Dynamic RAM
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
VG36648041(2)B
Parameter
Symbol
Test Conditions
-8H
-8L
-10
Unit Notes
Min Max Min Max Min Max
CL = 3
100
100
90 mA
1
Operating current
I
CC1
Burst length = 1
One bank active
CL = 2
95
95
85
t
RC
t
RC(MIN.)
, Io = 0mA
CKE
≥
V
Precharge standby
I
CC 2P
current in power
I
CC 2PS
down mode
Precharge standby
I
CC 2N
current in Non - power
down mode
CKE
CKE
CKE
CKE
≤
V
IH(MAX.)
t
CK
= 15ns
≤
V
IH(MAX.)
t
CK
=
∞
3
2
20
3
2
20
3
2
20
mA
≥
V
IH(MIN.)
t
CK
= 15ns
CKE
≥
V
IH(MIN.)
Input signals are
CS
changed one
time during 2 CLK cycles.
CKE
V
CKE
≥
V
IH(MIN.)
, tCK =
∞
CLK
≤
V
IL(MAX.)
Input signals are stable.
CKE
CKE
CKE
CKE
mA
I
CC 2NS
6
6
6
Active standby
current in power
down mode
Active standby
current in Nonpower
down mode
I
CC 3P
I
CC 3PS
I
CC 3N
≤
V
IL(MAX.)
, t
CK
= 15ns
≤
V
IL(MAX.)
, t
CK
=
∞
5
4
25
5
4
25
5
4
25
mA
≥
V
IH(MIN.)
, t
CK
= 15ns
CS
CKE
≥
V
IH(MIN.)
Input signals are changed
one time during 2CLKs.
CKE
CKE
mA
I
CC 3NS
≥
V
IH(MIN.)
t
CK
=
CLE
≤
V
IL(MAX.)
t
CK(MIN.)
≥
V
∞
10
10
10
Input signals are stable.
Operating current
(Burst mode)
Refresh current
Selfrefresh current
I
CC5
I
CC6
I
CC4
t
CK
CKE
CL = 3
CL = 2
CL = 3
CL = 2
-5
-5
160
145
130
125
2
5
5
0.4
2.4
V
TT
+ 0.8
2.4
V
TT
+ 0.8
-5
-5
160
125
130
125
2
5
5
0.4
2.4
V
TT
+ 0.8
-5
-5
135
105
110
105
2
5
5
0.4
mA
mA
uA
uA
V
V
V
4
4
5
3,6
mA
2
Io = 0mA
All banks Active
t
RC
= t
RC(MIN.)
lnput Ieakege current I
LI
Output Ieakege
current
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
I
LO
V
OL
V
OH
V
OL
V
OH
≤
0.2V
V
in
0,
CKE
≥
V
V
in
≤
V
DD
+ 0.3V
CKE
Pins not under test = 0V
V
out
CKE
0,
≥
V
V
out
≤
V
DD (MAX)
DQ# in H - Z., Dout disabled
l
OL
= 2mA
l
OH
= -2mA
l
OL
= 16mA
l
OH
= -16mA
V
TT
V
TT
V
TT
V
5
+ 0.8
+ 0.8
+ 0.8
Notes : 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open.
In addition to this, ICC1 is measured on condition that addresses are changed only one time duringt
CK(MIN.)
.
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open.
In addition to this, ICC4 is measured on condition that addresses are changed only one time during t
CK(MIN.)
.
3. ICC5 is measured on condition that addresses are changed only one time during t
CK(MIN.)
.
4. For LVTTL compatible, VG3664321(4)1.
5. For SSTL - 3 interface, VG3664321(4)2.
6. Refresh on every 15.6
µ
s.
Document : 1G5-0099
Rev.1
Page 6
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
