VIS
Parameter
Operating current
Symbol
I
CC1
Test Conditions
VG36644041DT / VG36648041DT / VG36641641DT
CMOS Synchronous Dynamic RAM
DC Characteristics 1
(Ta = 0 ~ 70°C, V
DD
= V
DDQ
= 3.3
±
0.3V, V
SS
= V
SSQ
= 0V, Ouput Open, unless otherwise noted)
Organization
x4
x8
x16
x4/x8/x16
x4/x8/x16
x4/x8/x16
-6
-
-
95
Limits (max.)
-7
-7L
75
75
75
75
85
85
2
1
20
mA
-8H
70
70
80
Unit Notes
One bank active
t
RC
= t
RC(MIN)
, t
CLK
= t
CLK(MIN)
,
BL = 1, CL=3
mA
1, 2
Precharge standby
I
CC2
P
CKE
≤
V
IL(MAX),
t
CK
= 15ns
current in power down
I
CC2
PS CKE
≤
V
IL(MAX)
, CLK
≤
V
IL(MAX)
mode
Precharge standby
I
CC2
N
CKE
≥
V
CC
- 0.2V
CS
current in non power
CKE
t
CK
= 15ns, CKE
≥
V
IH(MIN)
down mode
I
CC2
NS
CKE
≥
V
CC
- 0.2V
CS
CLK
≤
V
IL(MAX),
CKE
≥
V
IH(MIN)
CKE
V
All input signals are stable.
CKE
mA
3
x4/x8/x16
x4/x8/x16
x4/x8/x16
x4/x8/x16
15
7
5
30
mA
Active standby current I
CC3
P
in power down mode
I
CC3
PS
Active standby current I
CC3
N
in Nonpower down
mode
I
CC3
NS
≤
V
IL(MAX)
, t
CK
= 10ns
CKE
≤
V
IL(MAX)
, CLK
≤
V
IL(MAX)
CS
CKE
≥
V
CC
- 0.2V
CKE
t
CK
= 15ns, CKE
≥
V
IH(MIN)
CKE
≥
V
CC
- 0.2V
CS
CLK
≤
V
IL(MAX),
CKE
≥
V
IH(MIN)
CKE
V
All input signals are stable.
All banks active
t
CK
= t
CK(MIN)
, BL=4, CL=3
All banks active
t
RC
= t
RC(MIN)
, t
CLK
= t
CLK(MIN)
CKE
mA
mA
3
x4/x8/x16
x4
x8
x16
x4/x8/x16
x4/x8/x16
-
-
130
150
90
90
100
130
25
90
90
100
130
1
0.5
70
70
80
110
mA
Operating current
(Burst mode)
Refresh current
Self refresh current
NOTES
I
CC4
mA
mA
mA
mA
4
5
I
CC5
I
CC6
≤
0.2V
1. I
CC(max)
is specified at the output open condition.
2. -6 grade is available only on 4MX16 option.
3. Input signals are changed one time during 30ns.
4. Normal version: VG366440(80/16)41DT
5. Low power version: VG366440(80/16)41DTL
DC Characteristics 2
(Ta = 0 ~ 70°C, V
DD
= V
DDQ
= 3.3
±
0.3V , V
SS
= V
SSQ
= 0V, unless otherwise noted)
Parameter
Input leakage current (Inputs)
Output leakage current (I/O pins)
High level output voltage
Low level output voltage
Symbol
I
I (L)
I
O (L)
V
OH
V
OL
Test Condition
0
≤
V
IN
≤
V
DD(MAX)
Pins not under test = 0V
0
≤
V
OUT
≤
V
DD(MAX)
DQ# in H - Z., D
OUT
is disabled
I
OH
= -2mA
I
OL
= 2mA
Min
-5
-5
2.4
0.4
Max
5
5
Unit
uA
uA
V
V
Document :1G5-0177
Rev.2
Page 6
VML [ VANGUARD INTERNATIONAL SEMICONDUCTOR ]
