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WM8150 参数 Datasheet PDF下载

WM8150图片预览
型号: WM8150
PDF下载: 下载PDF文件 查看货源
内容描述: 单通道12位,且4位宽的输出CIS / CCD AFE [SINGLE CHANNEL 12 BIT CIS/CCD AFE WITH 4 BIT WIDE OUTPUT]
分类和应用: 输出元件
文件页数/大小: 24 页 / 271 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8150
ELECTRICAL CHARACTERISTICS
Production Data
Test Conditions
AVDD = DVDD1 = 5.0V, DVDD2 = 3.3V, AGND = DGND = 0V, T
A
= 25°C, MCLK = 16MHz unless otherwise stated.
PARAMETER
SYMBOL
TEST
CONDITIONS
Max Gain
Min Gain
V
IN
Gain = 0dB;
PGA[7:0] = 07(hex)
Gain = 0dB;
PGA[7:0] = 07(hex)
DNL
INL
Min Gain
Max Gain
VRT
VRB
VRX
V
RTB
1.55
1.15
0
-50
-50
10
10
0.5
2
0.25
0.70
2.70
1.45
1.65
1.25
1
20
1.86
VRLC = 0 to AVDD
4
V
RLCSTEP
V
RLCSTEP
V
RLCBOT
V
RLCBOT
V
RLCTOP
V
RLCTOP
AVDD = 5.0V
AVDD = 5.0V
AVDD = 5.0V
0.23
0.14
0.34
0.20
4.0
2.56
0.25
0.16
0.39
0.26
4.16
2.66
0.27
0.20
0.44
0.31
4.3
2.76
50
2
2
1
100
4.5
1.75
1.35
MIN
TYP
MAX
UNIT
Overall System Specification (including 12-bit ADC, PGA, Offset and CDS functions)
Full-scale input voltage range
(see Note 1)
Input signal limits (see Note 2)
Full-scale transition error
Zero-scale transition error
Differential non-linearity
Integral non-linearity
Total output noise
References
Upper reference voltage
Lower reference voltage
Input return bias voltage
Diff. reference voltage (VRT-VRB)
Output resistance VRT, VRB, VRX
VRLC/Reset-Level Clamp (RLC)
RLC switching impedance
VRLC short-circuit current
VRLC output resistance
VRLC Hi-Z leakage current
RLCDAC resolution
RLCDAC step size, RLCDAC = 0
RLCDAC step size, RLCDAC = 1
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 0
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 1
RLCDAC output voltage at
code F(hex) RLCDACRNG, = 0
RLCDAC output voltage at
code F(hex), RLCDACRNG = 1
Resolution
Differential non-linearity
Integral non-linearity
Step size
Output voltage
Code 00(hex)
Code FF(hex)
-247
+247
DNL
INL
mA
µA
bits
V/step
V/step
V
V
V
V
V
V
V
V
0.30
3.22
VDD
+50
+50
1
5
Vp-p
Vp-p
V
mV
mV
LSB
LSB
LSB rms
LSB rms
Offset DAC, Monotonicity Guaranteed
8
0.1
0.25
2.04
-260
+260
-273
+273
0.5
1
bits
LSB
LSB
mV/step
mV
mV
Notes:
1.
Full-scale input voltage
denotes the peak input signal amplitude that can be gained to match the ADC input
range.
2.
Input signal limits
are the limits within which the full-scale input voltage signal must lie.
w
PD Rev 3.0 November 2002
4