HUF75545P3, HUF75545S3, HUF75545S3S
Test Circuits and Waveforms
V
DS
BV
DSS
L
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
V
GS
DUT
t
P
R
G
-
I
AS
V
DD
t
P
V
DS
V
DD
+
0V
I
AS
0.01Ω
0
t
AV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
V
DS
R
L
V
DD
V
DS
V
GS
= 20V
V
GS
+
Q
g(TOT)
Q
g(10)
V
DD
V
GS
V
GS
= 2V
0
Q
g(TH)
Q
gs
I
g(REF)
0
Q
gd
V
GS
= 10V
-
DUT
I
g(REF)
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORMS
V
DS
t
ON
t
d(ON)
R
L
V
DS
+
t
OFF
t
d(OFF)
t
r
t
f
90%
90%
V
GS
V
DD
-
DUT
0
10%
90%
10%
R
GS
V
GS
V
GS
0
10%
50%
PULSE WIDTH
50%
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. SWITCHING TIME WAVEFORM
©2002 Fairchild Semiconductor Corporation
HUF75545P3 / HUF75545S3 / HUF75545S3S Rev. C