Ethernet: Three-Speed, MII Management
Table 27. MII Management DC Electrical Characteristics (continued)
Parameter
Input high current
Symbol
Conditions
Min
Max
Unit
IIH
IIL
LVDD = Max
LVDD = Max
VIN 1 = 2.1 V
VIN = 0.5 V
—
40
—
μA
μA
Input low current
–600
Note:
1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
8.3.2
MII Management AC Electrical Specifications
Table 28 provides the MII management AC timing specifications.
Table 28. MII Management AC Timing Specifications
At recommended operating conditions with LVDD is 3.3 V 5%.
Parameter/Condition
MDC frequency
Symbol 1
Min
Typ
Max
Unit
Notes
fMDC
tMDC
0.893
96
—
—
—
10.4
MHz
ns
2
MDC period
1120
MDC clock pulse width high
MDC to MDIO valid
MDC to MDIO delay
MDIO to MDC setup time
MDIO to MDC hold time
MDC rise time
tMDCH
32
—
ns
tMDKHDV
tMDKHDX
tMDDVKH
tMDDXKH
tMDCR
2*[1/(fccb_clk/8)]
ns
3
3
10
5
—
—
—
—
—
2*[1/(fccb_clk/8)]
ns
—
—
10
10
ns
0
ns
—
—
ns
MDC fall time
tMDHF
ns
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX
symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are
invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input
signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For
rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the system clock speed (that is, for a system clock of 267 MHz, the delay is 70 ns and for
a system clock of 333 MHz, the delay is 58 ns).
3. This parameter is dependent on the CCB clock speed (that is, for a CCB clock of 267 MHz, the delay is 60 ns and for a
CCB clock of 333 MHz, the delay is 48 ns).
4. Guaranteed by design.
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
32
Freescale Semiconductor
FREESCALE [ Freescale ]
