Local Bus
9.2
Local Bus AC Electrical Specifications
describes the general timing parameters of the local bus interface of the MPC8555E with the DLL
enabled.
Table 30. Local Bus General Timing Parameters - DLL Enabled
Parameter
Local bus cycle time
LCLK[n] skew to LCLK[m] or LSYNC_OUT
Input setup to local bus clock (except
LUPWAIT)
LUPWAIT input setup to local bus clock
Input hold from local bus clock (except
LUPWAIT)
LUPWAIT input hold from local bus clock
LALE output transition to LAD/LDP output
transition (LATCH hold time)
Local bus clock to output valid (except
LAD/LDP and LALE)
Local bus clock to data valid for LAD/LDP
LWE[0:1] = 00
LWE[0:1] = 11 (default)
LWE[0:1] = 00
LWE[0:1] = 11 (default)
Local bus clock to address valid for LAD
LWE[0:1] = 00
LWE[0:1] = 11 (default)
Output hold from local bus clock (except
LAD/LDP and LALE)
Output hold from local bus clock for
LAD/LDP
Local bus clock to output high Impedance
(except LAD/LDP and LALE)
LWE[0:1] = 00
LWE[0:1] = 11 (default)
LWE[0:1] = 00
LWE[0:1] = 11 (default)
LWE[0:1] = 00
LWE[0:1] = 11 (default)
t
LBKHOZ1
t
LBKHOX2
t
LBKHOX1
0.7
1.6
0.7
1.6
—
2.8
4.2
ns
5, 9
—
ns
3, 8
t
LBKHOV3
—
t
LBKHOV2
—
Configuration
7
Symbol
1
t
LBK
t
LBKSKEW
t
LBIVKH1
t
LBIVKH2
t
LBIXKH1
t
LBIXKH2
t
LBOTOT
t
LBKHOV1
Min
6.0
—
1.8
1.7
0.5
1.0
1.5
—
Max
—
150
—
—
—
—
—
2.3
3.8
2.5
4.0
2.6
4.1
—
ns
3, 8
ns
3, 8
ns
3, 8
Unit
ns
ps
ns
ns
ns
ns
ns
ns
Notes
2
7, 9
3, 4, 8
3, 4
3, 4, 8
3, 4
6
3, 8
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
34
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
