Local Bus
Table 30. Local Bus General Timing Parameters - DLL Enabled (continued)
Parameter
Local bus clock to output high impedance for
LAD/LDP
Configuration
7
LWE[0:1] = 00
LWE[0:1] = 11 (default)
Symbol
1
t
LBKHOZ2
Min
—
Max
2.8
4.2
Unit
ns
Notes
5, 9
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
(First two letters of functional block)(signal)(state)
(reference)(state)
for inputs and t
(First two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
LBIXKH1
symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the t
LBK
clock reference (K) goes
high (H), in this case for clock one(1). Also, t
LBKHOX
symbolizes local bus timing (LB) for the t
LBK
clock reference (K) to go
high (H), with respect to the output (O) going invalid (X) or output hold time.
2. All timings are in reference to LSYNC_IN for DLL enabled mode.
3. All signals are measured from OV
DD
/2 of the rising edge of LSYNC_IN for DLL enabled to 0.4
×
OV
DD
of the signal in
question for 3.3-V signaling levels.
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
6. The value of t
LBOTOT
is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by LBCR[AHD], and the number of local
bus buffer delays used as programmed at power-on reset with configuration pins LWE[0:1].
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at OV
DD
/2.
8. Guaranteed by characterization.
9. Guaranteed by design.
describes the general timing parameters of the local bus interface of the MPC8555E with the DLL
bypassed.
Table 31. Local Bus General Timing Parameters - DLL Bypassed
Parameter
Local bus cycle time
Internal launch/capture clock to LCLK
delay
LCLK[n] skew to LCLK[m] or LSYNC_OUT
Input setup to local bus clock (except
LUPWAIT)
LUPWAIT input setup to local bus clock
Input hold from local bus clock (except
LUPWAIT)
LUPWAIT input hold from local bus clock
LALE output transition to LAD/LDP output
transition (LATCH hold time)
Local bus clock to output valid (except
LAD/LDP and LALE)
Local bus clock to data valid for LAD/LDP
LWE[0:1] = 00
LWE[0:1] = 11 (default)
LWE[0:1] = 00
LWE[0:1] = 11 (default)
t
LBKLOV2
—
Configuration
7
Symbol
1
t
LBK
t
LBKHKT
t
LBKSKEW
t
LBIVKH1
t
LBIVKH2
t
LBIXKH1
t
LBIXKH2
t
LBOTOT
t
LBKLOV1
Min
6.0
1.8
—
5.2
5.1
-1.3
-0.8
1.5
—
Max
—
3.4
150
—
—
—
—
—
0.5
2.0
0.7
2.2
ns
3
Unit
ns
ns
ps
ns
ns
ns
ns
ns
ns
Notes
2
8
7, 9
3, 4
3, 4
3, 4
3, 4
6
3
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
35
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
