Local Bus
Table 31. Local Bus General Timing Parameters - DLL Bypassed (continued)
Parameter
Local bus clock to address valid for LAD
Configuration
7
LWE[0:1] = 00
LWE[0:1] = 11 (default)
Output hold from local bus clock (except
LAD/LDP and LALE)
Output hold from local bus clock for
LAD/LDP
Local bus clock to output high Impedance
(except LAD/LDP and LALE)
Local bus clock to output high impedance
for LAD/LDP
LWE[0:1] = 00
LWE[0:1] = 11 (default)
LWE[0:1] = 00
LWE[0:1] = 11 (default)
LWE[0:1] = 00
LWE[0:1] = 11 (default)
LWE[0:1] = 00
LWE[0:1] = 11 (default)
t
LBKLOZ2
—
t
LBKLOZ1
t
LBKLOX2
t
LBKLOX1
-2.7
-1.8
-2.7
-1.8
—
1.0
2.4
1.0
2.4
ns
5
ns
5
—
ns
3
Symbol
1
t
LBKLOV3
Min
—
Max
0.8
2.3
—
ns
3
Unit
ns
Notes
3
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
(First two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
(First two letters of functional block)(reference)(state)(signal)(state)
for outputs. For example, t
LBIXKH1
symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the t
LBK
clock reference (K) goes high (H), in this case for
clock one(1). Also, t
LBKHOX
symbolizes local bus timing (LB) for the t
LBK
clock reference (K) to go high (H), with respect to the
output (O) going invalid (X) or output hold time.
2. All timings are in reference to LSYNC_IN for DLL enabled mode.
3. All signals are measured from OV
DD
/2 of the rising edge of local bus clock for DLL bypass mode to 0.4
×
OV
DD
of the signal
in question for 3.3-V signaling levels.
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
6. The value of t
LBOTOT
is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by LBCR[AHD], and the number of local
bus buffer delays used as programmed at power-on reset with configuration pins LWE[0:1].
7. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at OV
DD
/2.
8. Guaranteed by characterization.
9. Guaranteed by design.
provides the AC test load for the local bus.
Output
Z
0
= 50
Ω
OV
DD
/2
R
L
= 50
Ω
Figure 15. Local Bus C Test Load
MPC8555E PowerQUICC™ III Integrated Communications Processor Hardware Specifications, Rev. 4
36
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
