ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
Pin Configuration
PLL_BW
CLK_INT
CLK_INC
**CLKREQ0#
VDD
GND
PCIEXT0
PCIEXC0
VDD
SMBDAT
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDDA
GNDA
IREF
**CLKREQ1#
VDD
GND
PCIEXT1
PCIEXC1
VDD
SMBCLK
Power Groups
Note:
Pins preceeded by '**' have internal
120K ohm pull down resistors
20-pin SSOP & TSSOP
Pin Description
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
PIN NAME
PLL_BW
CLK_INT
CLK_INC
**CLKREQ0#
VDD
GND
PCIEXT0
PCIEXC0
VDD
SMBDAT
SMBCLK
VDD
PCIEXC1
PCIEXT1
GND
VDD
**CLKREQ1#
PIN TYPE
INPUT
INPUT
INPUT
INPUT
POWER
POWER
OUTPUT
OUTPUT
POWER
I/O
INPUT
POWER
OUTPUT
OUTPUT
POWER
POWER
INPUT
DESCRIPTION
3.3V input for selecting PLL Band Width
0 = low, 1= high
"True" reference clock input.
"Complementary" reference clock input.
Output enable for SRC/PCI Express output pair '0'
0 = enabled, 1 = tri-stated
Power supply, nominal 3.3V
Ground pin.
True clock of differential PCI_Express pair.
Complement clock of differential PCI_Express pair.
Power supply, nominal 3.3V
Data pin of SMBUS circuitry, 5V tolerant
Clock pin of SMBUS circuitry, 5V tolerant
Power supply, nominal 3.3V
Complement clock of differential PCI_Express pair.
True clock of differential PCI_Express pair.
Ground pin.
Power supply, nominal 3.3V
Output enable for SRC/PCI Express output pair '1'
0 = enabled, 1 = tri-stated
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
18
19
20
IREF
GNDA
VDDA
ICS9DB102
Pin Number
VDD
GND
5,9,12,16
6,15
9
6
20
19
20
19
Description
PCI Express Outputs
SMBUS
IREF
Analog VDD & GND for PLL core
OUTPUT
POWER
POWER
Note:
Pins preceeded by '**' have internal 120K ohm pull down resistors
IDT
®
Two Output Differential Buffer for PCIe Gen1 & Gen2
852
REV K 04/01/10
2
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
