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9DB102BGLFT 参数 Datasheet PDF下载

9DB102BGLFT图片预览
型号: 9DB102BGLFT
PDF下载: 下载PDF文件 查看货源
内容描述: 两个输出差分缓冲器,用于PCIe一代和第二代 [Two Output Differential Buffer for PCIe Gen1 & Gen2]
分类和应用: 时钟驱动器逻辑集成电路光电二极管PC
文件页数/大小: 13 页 / 186 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
Electrical Characteristics - PCIEX 0.7V Current Mode Differential Pair
T
A
= Tambient; V
DD
= 3.3 V +/-5%; C
L
PARAMETER
SYMBOL
Current Source Output
Zo
Impedance
Voltage High
VHigh
Voltage Low
VLow
Max Voltage
Vovs
Min Voltage
Vuds
Crossing Voltage (abs) Vcross(abs)
Crossing Voltage (var)
Long Accuracy
Average period
Absolute min period
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
Input to Output Delay
Duty Cycle
Output-to-Output Skew
Jitter, Cycle to cycle
1
=2pF, R
S
=33.2 , R
P
=49.9 , I
REF
= 475
CONDITIONS
MIN
V
O
= V
x
Statistical measurement on
single ended signal using
Measurement on single ended
signal using absolute value.
3000
660
-150
-300
250
Variation of crossing over all
edges
see Tperiod min-max values
100.00MHz nominal
100.00MHz spread
100.00MHz nominal/spread
V
OL
= 0.175V, V
OH
= 0.525V
V
OH
= 0.525V V
OL
= 0.175V
TYP
MAX
UNITS NOTES
1
850
150
1150
350
12
550
140
0
10.0030
10.0533
700
700
125
125
150
4.2
55
25
35
30
mV
mV
mV
mV
ppm
ns
ns
ns
ps
ps
ps
ps
ps
ns
%
ps
ps
ps
1,3
1,3
1,3
1,3
1,3
1,3
1,2
2
2
1,2
1
1
1
1
1
1
1
1
1
1
d-Vcross
ppm
Tperiod
Tabsmin
t
r
t
f
d-t
r
d-t
f
t
pd
t
pdbyp
d
t3
t
sk3
t
jcyc-cyc
t
jcyc-cycbyp
9.9970
9.9970
9.8720
175
175
30
30
PLL Mode.
Bypass mode
Measurement from differential
wavefrom
V
T
= 50%
PLL mode. Measurement from
differential wavefrom
Additve Jitter in Bypass Mode
0
3.7
45
2
.
Guaranteed by design, not 100% tested in production.
The 9DB102 does not add a ppm error to the input clock
3
I
REF
= V
DD
/(3xR
R
). For R
R
= 475 (1%), I
REF
= 2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50 .
IDT
®
Two Output Differential Buffer for PCIe Gen1 & Gen2
852
REV K 04/01/10
4