ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
Absolute Max
Symbol
VDDA
VDD
Ts
Tcase
ESD prot
Parameter
3.3V Core Supply Voltage
3.3V Output Supply Voltage
Storage Temperature
Case Temperature
Input ESD protection
human body model
Min
GND - 0.5
-65
Max
V
DD
+ 0.5V
V
DD
+ 0.5V
150
115
Units
V
V
C
°
C
V
°
2000
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= Tambient; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER
Tambient
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
Tambcom
Tambind
V
IH
V
IL
I
IH
I
IL1
Input Low Current
I
IL2
Operating Supply Current
Input Frequency
3
Pin Inductance
1
Input Capacitance
1
Clk Stabilization
1,2
Modulation Frequency
Spread Spectrum Modulation
Frequency
PLL Bandwidth
SMBus Voltage
Low-level Output Voltage
Current sinking at V
OL
= 0.4 V
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
Clock/Data Fall Time
1
CONDITIONS
Commercial range
Industrial range
3.3 V +/-5%
3.3 V +/-5%
V
IN
= V
DD
V
IN
= 0 V; Inputs with no pull-
up resistors
V
IN
= 0 V; Inputs with pull-up
resistors
Full Active, C
L
= Full load;
all differential pairs tri-stated
V
DD
= 3.3 V
Logic Inputs
Output pin capacitance
From V
DD
Power-Up to 1st
clock
Triangular Modulation
Lexmark Modulation
PLL Bandwidth when
PLL_BW=0
PLL Bandwidth when
PLL_BW=1
MIN
0
-40
2
V
SS
- 0.3
-5
-5
-200
TYP
MAX
70
85
V
DD
+ 0.3
0.8
5
UNITS NOTES
°
C
°
C
V
V
uA
uA
uA
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
I
DD3.3OP
F
i
L
pin
C
IN
C
OUT
T
STAB
80
75
27
100
100
50
105
7
5
4.5
1.8
mA
mA
MHz
nH
pF
pF
ms
kHz
KHz
KHz
MHz
30
25
400
1.2
2.7
33
45
f
MOD
BW
V
DD
V
OLSMBUS
I
PULLUP
T
RI2C
T
FI2C
@ I
PULLUP
SMBus SDATA pin
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
5.5
0.4
4
1000
300
V
V
mA
ns
ns
Guaranteed by design and characterization, not 100% tested in production.
IDT
®
Two Output Differential Buffer for PCIe Gen1 & Gen2
852
REV K 04/01/10
3
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
