bq3285LF
VPFD (2.53V typical), the bq3285LF write-protects the RS0–RS3 - Frequency Select
clock and storage registers. The power source is switched
to BC when VCC is less than VPFD and BC is greater than
VPFD, or when VCC is less than VBC and VBC is less than
VPFD. RTC operation and storage data are sustained by a
valid backup energy source. When VCC is above VPFD, the
power source is VCC. Write-protection continues for tCSR
7
-
6
-
5
-
4
-
3
2
1
0
RS3 RS2 RS1 RS0
These bits select the periodic interrupt rate, as shown in
Table 3.
time after VCC rises above VPFD
.
OS0–OS2 - Oscillator Control
Control/Status Registers
7
-
6
5
4
3
-
2
-
1
-
0
-
The four control/status registers of the bq3285LF are ac-
cessible regardless of the status of the update cycle (see
Table 4).
OS2 OS1 OS0
These three bits control the state of the oscillator and
divider stages. A pattern of 010 or 011 enables RTC op-
eration by turning on the oscillator and enabling the fre-
quency divider. This pattern must be set to turn the os-
cillator on and to ensure that the bq3285LF keeps time
in battery-backup mode. A pattern of 11X turns the os-
cillator on, but keeps the frequency divider disabled.
When 010 is written, the RTC begins its first update af-
ter 500ms.
Register A
Register A Bits
7
6
5
4
3
2
1
0
UIP OS2 OS1 OS0 RS3 RS2 RS1 RS0
Register A programs:
UIP - Update Cycle Status
n
n
n
The frequency of the periodic event rate.
Oscillator operation.
7
6
-
5
-
4
-
3
-
2
-
1
-
0
-
UIP
Time-keeping
This read-only bit is set prior to the update cycle. When
UIP equals 1, an RTC update cycle may be in progress.
UIP is cleared at the end of each update cycle. This bit
is also cleared when the update transfer inhibit (UTI)
bit in register B is 1.
Register A provides:
n
Status of the update cycle.
Table 4. Control/Status/Index Registers
Bit Name and State on Reset
Loc.
Reg. (Hex) Read Write
7 (MSB)
6
5
4
3
2
1
0 (LSB)
A
B
0A
0B
0C
0D
7E
7F
Yes Yes1 UIP na OS2 na OS1 na OS0 na RS3 na RS2 na RS1 na RS0 na
Yes Yes UTI na PIE
0
0
0
0
0
AIE
AF
0
0
UIE
UF
0
0
-
-
0
0
DF na HF na DSE na
na
C
Yes No INTF
Yes Yes2 VRT na
0
PF
-
-
-
0
-
0
D
DA5 na DA4 na DA3 na DA2 na DA1 na DA0 na
SI
EI
Yes No NMI
Yes No CENT
0
0
SI6
EI6
SI5
EI5
0
0
SI4
EI4
0
0
SI3
EI3
0
0
SI2
EI2
0
0
SI1
EI1
0
0
SI0
EI0
0
0
Notes:
na = not affected.
x = unknown
1. Except bit 7.
2. Except bits 6 and 7.
8
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