bq3285LF
On the next update cycle, the RTC updates all 10 bytes
in the selected format.
Each of the three interrupt events is enabled by an indi-
vidual interrupt-enable bit in register B. When an event
occurs, its event flag bit in register C is set. If the corre-
sponding event enable bit is also set, then an interrupt
request is generated. The interrupt request flag bit
(INTF) of register C is set with every interrupt request.
Reading register C clears all flag bits, including INTF,
and makes INT high-impedance.
32kHz Output
The bq3285LF provides for a 32.768kHz output, and the
output is always active whenever VCC is valid (VPFD
+
tCSR). The bq3285LF output is not affected by the bit
settings in Register A. Time-keeping aspects, however,
still require setting OS0-OS2.
Two methods can be used to process bq3285LF interrupt
events:
n
n
Enable interrupt events and use the interrupt
request output to invoke an interrupt service routine.
Interrupts
Do not enable the interrupts and use a polling routine
to periodically check the status of the flag bits.
The bq3285LF allows three individually selected inter-
rupt events to generate an interrupt request. These
three interrupt events are:
The individual interrupt sources are described in detail
in the following sections.
n
n
The periodic interrupt, programmable to occur once
every 122µs to 500ms.
Periodic Interrupt
The alarm interrupt, programmable to occur once per
second to once per day, is active in battery-backup
mode, providing a “wake-up” feature.
If the periodic interrupt event is enabled by writing a 1
to the periodic interrupt enable bit (PIE) in register C,
an interrupt request is generated once every 122µs to
500ms. The period between interrupts is selected with
bits RS3-RS0 in register A (see Table 3).
n
The update-ended interrupt, which occurs at the end
of each update cycle.
Table 3. Periodic Interrupt Rate
Register A Bits
Periodic Interrupt
Period Units
None
3.90625
OSC2
OSC1
OSC0
RS3
0
RS2
0
RS1
0
RS0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
ms
ms
µs
0
0
1
0
7.8125
122.070
244.141
488.281
976.5625
1.95315
3.90625
7.8125
15.625
31.25
0
0
1
1
0
1
0
0
µs
0
1
0
1
µs
0
1
1
0
µs
0
1
1
1
ms
ms
ms
ms
ms
ms
ms
ms
ms
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
62.5
1
1
0
1
125
1
1
1
0
250
1
1
1
1
500
same as above defined
by RS3–RS0
0
1
1
X
X
X
X
6
TI [ TEXAS INSTRUMENTS ]
