bq3285LF
inhibit bit (UTI) in register B is 0, then an interrupt re-
quest is generated at the end of each update cycle.
Alarm Interrupt
The alarm interrupt is active in battery-backup mode,
providing a “wake-up” capability. During each update
cycle, the RTC compares the day-of-the-month, hours,
minutes, and seconds bytes with the four corresponding
alarm bytes. If a match of all bytes is found, the alarm
interrupt event flag bit, AF in register C, is set to 1. If
the alarm event is enabled, an interrupt request is gen-
erated.
Accessing RTC bytes
The EXTRAM pin must be low to access the RTC regis-
ters. Time and calendar bytes read during an update
cycle may be in error. Three methods to access the time
and calendar bytes without ambiguity are:
n
Enable the update interrupt event to generate
interrupt requests at the end of the update cycle.
The interrupt handler has a maximum of 999ms to
access the clock bytes before the next update cycle
begins (see Figure 3).
An alarm byte may be removed from the comparison by
setting it to a “don't care” state. The seconds, minutes,
and hours alarm bytes are set to a “don't care” state by
writing a 1 to each of its two most-significant bits. The
day-of-the-month alarm byte is set to a “don’t care” state
by setting DA5–DA0, in register D, to all zeros. A “don't
care” state may be used to select the frequency of alarm
interrupt events as follows:
n
n
Poll the update-in-progress bit (UIP) in register A. If
UIP = 0, the polling routine has a minimum of tBUC
time to access the clock bytes (see Figure 3).
n
n
n
n
n
If none of the four alarm bytes is “don't care,” the
frequency is once per month, when day-of-the-month,
hours, minutes, and seconds match.
Use the periodic interrupt event to generate
interrupt requests every tPI time, such that UIP = 1
always occurs between the periodic interrupts. The
interrupt handler has a minimum of tPI/2 + tBUC
time to access the clock bytes (see Figure 3).
If only the day-of-the-month alarm byte is “don’t
care”, the frequency is once per day, when hours,
minutes, and seconds match.
Oscillator Control
If only the day-of-the-month and hour alarm byte is
“don't care,” the frequency is once per hour, when
minutes and seconds match.
When power is first applied to the bq3285LF and VCC is
above VPFD, the internal oscillator and frequency divider
are turned on by writing a 010 pattern to bits 4 through
6 of register A. A pattern of 11X turns the oscillator on
but keeps the frequency divider disabled. Any other pat-
tern to these bits keeps the oscillator off. A pattern of
010 must be set for the bq3285LF to keep time in bat-
tery backup mode.
If only the day-of-the-month, hour and minute alarm
bytes are “don't care,” the frequency is once per
minute, when seconds match.
If the day-of-the-month, hour, minute, and second
alarm bytes are “don't care,” the frequency is once per
second.
Update Cycle Interrupt
Power-Down/Power-Up Cycle
The update cycle ended flag bit (UF) in register C is set to
a 1 at the end of an update cycle. If the update interrupt
enable bit (UIE) of register B is 1, and the update transfer
The bq3285LF continuously monitors VCC for out-of-
tolerance. During a power failure, when VCC falls below
1 Sec.
UIP
t
UC
(t )/2
Pl
(t )/2
Pl
t
t
BUC
Pl
PF
UF
T3285L02.eps
Figure 3. Update-Ended/Periodic Interrupt Relationship
7
TI [ TEXAS INSTRUMENTS ]
