MSP430G2x52
MSP430G2x12
SLAS722B
–
DECEMBER 2010
–
REVISED MARCH 2011
Functional Block Diagram, MSP430G2x52
XIN XOUT
DVCC
DVSS
P1.x
8
P2.x
up to 8
ACLK
Clock
System
MCLK
Flash
SMCLK
8KB
4KB
2KB
1KB
MAB
MDB
256B
256B
256B
128B
10-Bit
8 Ch.
Autoscan
1 ch DMA
RAM
ADC
Port P1
8 I/O
Interrupt
capability
pullup/down
resistors
Port P2
up to 8 I/O
Interrupt
capability
pullup/down
resistors
16MHz
CPU
incl. 16
Registers
Emulation
2BP
JTAG
Interface
Spy-Bi
Wire
RST/NMI
Brownout
Protection
USI
Comp_A+
8 Channels
Watchdog
WDT+
15-Bit
Timer0_A3
3 CC
Registers
Universal
Serial
Interface
SPI, I2C
NOTE: Port P2. Two pins are available on the 14/16-pin package options. Eight pins are available on the 20-pin package
options.
Functional Block Diagram, MSP430G2x12
XIN XOUT
DVCC
DVSS
P1.x
8
P2.x
up to 8
ACLK
Clock
System
Flash
SMCLK
8KB
4KB
2KB
1KB
RAM
256B
Port P1
8 I/O
Interrupt
capability
pullup/down
resistors
Port P2
up to 8 I/O
Interrupt
capability
pullup/down
resistors
MCLK
16MHz
CPU
incl. 16
Registers
MAB
MDB
Emulation
2BP
JTAG
Interface
Spy-Bi
Wire
RST/NMI
Brownout
Protection
USI
Comp_A+
8 Channels
Watchdog
WDT+
15-Bit
Timer0_A3
3 CC
Registers
Universal
Serial
Interface
SPI, I2C
NOTE: Port P2. Two pins are available on the 14/16-pin package options. Eight pins are available on the 20-pin package
options.
4
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2010–2011, Texas Instruments Incorporated
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