eZ80F91 ASSP
Product Specification
124
capture event from overwriting the high byte between the two reads and generating an
invalid capture value. The capture value registers are read-only.
A capture flag (ICA or ICB) in the TMRx_IIR register is set whenever a capture event
occurs. Setting the interrupt identification register bit TMRx_IER[IRQ_ICx_EN] enables
the capture event to generate a timer interrupt. The port pins must be configured as alter-
nate functions, see the
Output Compare
The output compare function reverses the input capture function. Rather than store a timer
value when an external event occurs, OUTPUT COMPARE Mode waits until the timer
reaches a specified value, then generates an external event. Although the same base timer
is used, up to four separate external pins are driven each with its own compare value.
To use OUTPUT COMPARE Mode, the CPU must first configure the basic timer parame-
ters. Then it must load up to four 16-bit compare values into the four TMR3_OCx Register
pairs. Next, it must load the TMR3_ OC_CTL2 Register to specify the event that occurs
on comparison. You can select the following events: SET, CLEAR, and TOGGLE.
Finally, the CPU must enable OUTPUT COMPARE Mode by asserting
TMR3_OC_CTL1[OC_EN].
The initial value for the OCx pins in OUTPUT COMPARE Mode is 0 by default. It is pos-
sible to initialize this value to 1 or force a value at a later time. Setting the
TMR3_OC_CTL2[OCx_MODE] value to 0 forces the OCx pin to the selected state pro-
vided by the TMR3_OC_CTL1[OCx_INIT] bits. Regardless of any compare events, the
pin stays at the forced value until OCx_MODE is changed. After release, it retains the
forced value until modified by an OUTPUT COMPARE event.
Asserting TMR3_OC_CTL1[MAST_MODE] selects MASTER MODE for all OUTPUT
COMPARE events and sets output 0 as the master. As a result, outputs 1, 2, and 3 are
caused to disregard output-specific configuration and comparison values and instead
mimic the current settings for output 0.
The OCx bits in the TMR3_IIR Register are set whenever the corresponding timer com-
pares occur. TMR3_IER[IRQ_OCx_EN] allows the compare event to generate a timer
interrupt.
Timer Port Pin Allocation
The eZ80F91 device timers interface to the outside world via Ports A and B. These ports
are also used for GPIO as well as other assorted functions. Table 53 lists the timer pins and
their respective functions.
PS027004-0613
PRELIMINARY
Programmable Reload Timers
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