eZ80F91 ASSP
Product Specification
123
requirements. However, INPUT CAPTURE and OUTPUT COMPARE modes run simul-
taneously.
Timers with specialty modes offer multiple ways to generate an interrupt. When the inter-
rupt controller services a timer interrupt, the software must read the Timer Interrupt Iden-
tification Registers (TMRx_IIR) to determine the causes for an interrupt request. This
register is cleared each time it is read, allowing subsequent events to be identified without
interference from prior events.
Event Counter
When a timer is configured to take its input from a port input pin (ECx), it functions as an
event counter. For event counting, the clock prescaler is automatically bypassed and edges
(events) cause the timer to decrement. You must select the rising or the falling edge for
counting. Also, the port pins must be configured as inputs.
Input sampling on the port pins results in the counter being updated on the third rising
edge of the system clock after the edge event occurs at the port pin. Due to sampling, the
frequency of the event input is limited to one-half the system clock frequency under ideal
conditions. In practice, the event frequency must be less than this value due to duty cycle
variation and system clock jitter.
This EVENT COUNT Mode is identical to basic timer operation, except for the clock
source. Therefore, interrupts are managed in the same manner.
RTC Oscillator Input
When the timer clock source is the Real-Time Clock signal, the timer functions just as it
does in EVENT COUNT Mode, except that it samples the internal RTC clock rather than
the ECx pin.
Input Capture
INPUT CAPTURE Mode allows the CPU to determine the timing of specified events on a
set of external pins.
A timer intended for use in INPUT CAPTURE Mode is setup the same way as in BASIC
Mode, with one exception. The CPU must also write the TMRx_CAP_CTL Register to
select the edge on which to capture: rising, falling, or both. When one of these events
occurs on an input capture pin, the current 16 bit timer value is latched into the capture
value register pair (TMRx_CAP_A or TMRx_CAP_B depending on the IC pin exhibiting
the event).
Reading the low byte of the register pair causes the timer to ignore other capture events on
the associated external pin until the high byte is read. This instance prevents a subsequent
PS027004-0613
PRELIMINARY
Programmable Reload Timers
ZILOG [ ZILOG, INC. ]
