eZ80F91 ASSP
Product Specification
126
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Timer Reload Registers (TMRx_RR_H and TMRx_RR_L)
The Timer Data Register is read-only when the Timer Reload Register is write-only. The
address space for these two registers is shared.
Register Set for Capture in Timer 1
In addition to the basic register set, Timer 1 uses the following five registers for its INPUT
CAPTURE Mode:
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Capture Control Register (TMR1_CAP_CTL)
Capture Value Registers (TMR1_CAP_B_H, TMR1_CAP_B_L, TMR1_CAP_A_H,
TMR1_CAP_A_L)
Register Set for Capture/Compare/PWM in Timer 3
In addition to the basic register set, Timer 3 uses 19 registers for INPUT CAPTURE,
OUTPUT COMPARE, and PWM modes. PWM and capture/compare functions cannot be
used simultaneously so, their register address space is shared. INPUT CAPTURE and
OUTPUT COMPARE are used concurrently and their address space is not shared.
The INPUT CAPTURE Mode registers are equivalent to those used in Timer 1 above
(substitute TMR3 for TMR1).
OUTPUT COMPARE Mode uses the following nine registers:
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Output Compare Control Registers
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TMR3_OC_CTL1
TMR3_OC_CTL2
Compare Value Registers
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–
–
–
–
–
–
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TMR3_OC3_H
TMR3_OC3_L
TMR3_OC2_H
TMR3_OC2_L
TMR3_OC1_H
TMR3_OC1_L
TMR3_OC0_H
TMR3_OC0_L
Multiple PWM Mode uses the following 19 registers:
PWM Control Registers
TMR3_PWM_CTL1
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PS027004-0613
P R E L I M I N A R Y
Programmable Reload Timers
ZILOG [ ZILOG, INC. ]
