FDD3672现货热卖使用介绍供应商报价哪里找芯片批发报价-中国IC网-芯三七

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产品型号FDD3672的概述

芯片FDD3672的概述 FDD3672是一款由Fairchild Semiconductor（现为NXP Semiconductors的一部分）生产的双N沟道MOSFET，其设计主要用于电源管理、电机驱动和其他高效能的电子应用中。这款芯片因其良好的开关性能和可靠的热特性，广泛应用于消费电子、工业设备和汽车电子等领域。FDD3672以其低导通电阻和高开关频率，满足了现代电子设备对高效率和轻量化的需求。芯片FDD3672的详细参数 FDD3672的主要电气参数包括： - 最大漏极源极电压(VDS): 30V - 最大漏极电流(ID): 60A - 导通电阻(RDS(on)): 0.015 Ohms（典型值，在10V栅极驱动下） - 栅源阈值电压(VGS(th)): 2V至4V - 输入电容(Ciss): 2400pF - 输出电容(Coss): 80pF - 反向恢复时间(Trr)：下...

产品型号FDD3672的Datasheet PDF文件预览

June 2002

FDD3672

N-Channel UltraFET^®Trench MOSFET

100V, 44A, 28mΩ

Features

Applications

•

r_DS(ON)= 24mΩ (Typ.), V_GS= 10V, I_D= 44A

Q_g(tot) = 24nC (Typ.), V_GS= 10V

Low Miller Charge

•

DC/DC converters and Off-Line UPS

Distributed Power Architectures and VRMs

Primary Switch for 24V and 48V Systems

High Voltage Synchronous Rectifier

Direct Injection / Diesel Injection System

42V Automotive Load Control

Low Qrr Body Diode

Optimized efficiency at high frequencies

UIS Capability (Single Pulse and Repetitive Pulse)

Qualified to AEC Q101

Electronic Valve Train System

Formerly developmental type 82760

DRAIN

(FLANGE)

GATE

SOURCE

TO-252AB

FDD SERIES

MOSFET Maximum Ratings T_C= 25°C unless otherwise noted

Symbol

V_DSS

V_GS

Parameter

Ratings

100

Units

Drain to Source Voltage

Gate to Source Voltage

Drain Current

±20

Continuous (T_C= 25^oC, V_GS= 10V)

Continuous (T_C= 100^oC, V_GS= 10V)

Continuous (T_amb= 25^oC, V_GS= 10V, R_θJA= 52^oC/W)

Pulsed

I_D

6.5

Figure 4

120

E_AS

Single Pulse Avalanche Energy (Note 1)

Power dissipation

Derate above 25^oC

W/^oC

^oC

135

P_D

0.9

T_J, T_STG

Operating and Storage Temperature

-55 to 175

Thermal Characteristics

R_θJC

R_θJA

Thermal Resistance Junction to Case TO-252

1.11

100

^oC/W

Thermal Resistance Junction to Ambient TO-252

Thermal Resistance Junction to Ambient TO-252, 1in²copper pad area

This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a

copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/

Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html.

All Fairchild Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems

certification.

FDD3672 Rev. A

Package Marking and Ordering Information

Device Marking

Device

Package

Reel Size

Tape Width

Quantity

FDD3672

TO-252AA

330mm

16mm

2500 units

Electrical Characteristics ^T_C= 25°C unless otherwise noted

Symbol

Parameter

Test Conditions

Min

Typ

Max

Units

Off Characteristics

B_VDSS

Drain to Source Breakdown Voltage

Zero Gate Voltage Drain Current

Gate to Source Leakage Current

I_D= 250µA, V_GS= 0V

100

_DS= 80V

I_DSS

µA

V_GS= 0V

T_C= 150^oC

250

±100

I_GSS

V_GS= ±20V

On Characteristics

V_GS(TH)

Gate to Source Threshold Voltage

V_GS= V_DS, I_D= 250µA

_D= 44A, V_GS= 10V

0.024 0.028

0.031 0.047

0.054 0.068

r_DS(ON)

Drain to Source On Resistance

I_D= 21A, V_GS= 6V,

I_D=44A, V_GS=10V, T_C=175^oC

Ω

Dynamic Characteristics

C_ISS

Input Capacitance

1710

247

V_DS= 25V, V_GS= 0V,

f = 1MHz

C_OSS

C_RSS

Q_g(TOT)

Q_g(TH)

Q_gs

Output Capacitance

Reverse Transfer Capacitance

Total Gate Charge at 10V

Threshold Gate Charge

V_GS= 0V to 10V

4.5

V_GS= 0V to 2V

V_DD= 50V

_D= 44A

I_g= 1.0mA

Gate to Source Gate Charge

Gate Charge Threshold to Plateau

Gate to Drain “Miller” Charge

8.6

5.6

Q_gs2

Q_gd

Resistive Switching Characteristics (V_GS= 10V)

t_ON

t_d(ON)

t_r

Turn-On Time

Turn-On Delay Time

Rise Time

104

_DD= 50V, I_D= 44A

_GS= 10V, R_GS= 11.0Ω

t_d(OFF)

t_f

Turn-Off Delay Time

Fall Time

t_OFF

Turn-Off Time

104

Drain-Source Diode Characteristics

_SD= 44A

1.25

1.0

V_SD

Source to Drain Diode Voltage

I_SD= 21A

t_rr

Reverse Recovery Time

Reverse Recovery Charge

I_SD= 44A, dI_SD/dt =100A/µs

Q_RR

Notes:

1: Starting T = 25°C, L = 0.6mH, I = 20A.

2: Pulse Width = 100s

FDD3672 Rev. A

Typical Characteristics T_C= 25°C unless otherwise noted

1.2

= 10V

1.0

0.8

0.6

0.4

0.2

150

100

175

125

100

125

150

175

, CASE TEMPERATURE ( C)

Figure 1. Normalized Power Dissipation vs

Ambient Temperature

Figure 2. Maximum Continuous Drain Current vs

Case Temperature

DUTY CYCLE - DESCENDING ORDER

0.5

0.2

0.1

0.05

0.02

0.01

0.1

NOTES:

DUTY FACTOR: D = t /t

SINGLE PULSE

PEAK T = P x Z

x R

+ T

θJC

θJC C

0.01

-5

-4

-3

-2

-1

t, RECTANGULAR PULSE DURATION (s)

Figure 3. Normalized Maximum Transient Thermal Impedance

500

= 25 C

TRANSCONDUCTANCE

MAY LIMIT CURRENT

IN THIS REGION

FOR TEMPERATURES

ABOVE 25 C DERATE PEAK

CURRENT AS FOLLOWS:

175 - T

150

I = I

= 10V

100

-5

-4

-3

-2

-1

t, PULSE WIDTH (s)

Figure 4. Peak Current Capability

FDD3672 Rev. A

Typical Characteristics T_C= 25°C unless otherwise noted

300

100

If R = 0

= (L)(I )/(1.3*RATED BV

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

- V

)

DSS

If R ≠ 0

= 15V

= (L/R)ln[(I *R)/(1.3*RATED BV

- V ) +1]

DSS

STARTING T = 25 C

= 175 C

= 25 C

STARTING T = 150 C

= -55 C

0.001

0.01

0.1

3.5

4.0

4.5

5.0

5.5

6.0

6.5

, TIME IN AVALANCHE (ms)

, GATE TO SOURCE VOLTAGE (V)

NOTE: Refer to Fairchild Application Notes AN7514 and AN7515

Figure 5. Unclamped Inductive Switching

Capability

Figure 6. Transfer Characteristics

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

= 25 C

= 10V

= 7V

= 6V

PULSE DURATION = 80µs

DUTY CYCLE = 0.5% MAX

= 10V

= 5V

2.0

I , DRAIN CURRENT (A)

0.5

1.0

1.5

2.5

3.0

, DRAIN TO SOURCE VOLTAGE (V)

Figure 7. Saturation Characteristics

Figure 8. Drain to Source On Resistance vs Drain

Current

2.5

1.2

PULSE DURATION = 80µs

= V , I = 250µA

DS D

DUTY CYCLE = 0.5% MAX

2.0

1.5

1.0

0.5

1.0

0.8

0.6

0.4

= 10V, I = 44A

-80

-40

120

160

200

-80

-40

120

160

200

T , JUNCTION TEMPERATURE ( C)

Figure 9. Normalized Drain to Source On

Resistance vs Junction Temperature

Figure 10. Normalized Gate Threshold Voltage vs

Junction Temperature

FDD3672 Rev. A

Typical Characteristics T_C= 25°C unless otherwise noted

1.2

1.1

1.0

0.9

3000

1000

= 250µA

= C + C

GS GD

ISS

+ C

OSS

DS GD

= C

RSS

100

= 0V, f = 1MHz

-80

-40

120

160

200

0.1

, DRAIN TO SOURCE VOLTAGE (V)

100

T , JUNCTION TEMPERATURE ( C)

Figure 11. Normalized Drain to Source

Breakdown Voltage vs Junction Temperature

Figure 12. Capacitance vs Drain to Source

Voltage

= 50V

WAVEFORMS IN

DESCENDING ORDER:

= 44A

= 21A

Q , GATE CHARGE (nC)

Figure 13. Gate Charge Waveforms for Constant Gate Currents

FDD3672 Rev. A

Test Circuits and Waveforms

DSS

VARY t TO OBTAIN

REQUIRED PEAK I

DUT

0.01Ω

Figure 14. Unclamped Energy Test Circuit

Figure 15. Unclamped Energy Waveforms

g(TOT)

= 10V

= 2V

DUT

gs2

g(REF)

g(TH)

g(REF)

Figure 16. Gate Charge Test Circuit

Figure 17. Gate Charge Waveforms

OFF

d(OFF)

d(ON)

90%

10%

DUT

90%

50%

PULSE WIDTH

10%

Figure 18. Switching Time Test Circuit

Figure 19. Switching Time Waveforms

FDD3672 Rev. A

Thermal Resistance vs. Mounting Pad Area

The maximum rated junction temperature, T_JM, and the

125

thermal resistance of the heat dissipating path determines

the maximum allowable device power dissipation, P_DM, in an

= 33.32+ 23.84/(0.268+Area) EQ.2

= 33.32+ 154/(1.73+Area) EQ.3

θJA

application.

Therefore the application’s ambient

θJA

100

temperature, T_A(^oC), and thermal resistance R_θJA(^oC/W)

must be reviewed to ensure that T_JMis never exceeded.

Equation 1 mathematically represents the relationship and

serves as the basis for establishing the rating of the part.

– T )

(EQ. 1)

= -----------------------------

R_{θ JA}

In using surface mount devices such as the TO-252

package, the environment in which it is applied will have a

significant influence on the part’s current and maximum

power dissipation ratings. Precise determination of P_DMis

complex and influenced by many factors:

0.01

(0.0645)

0.1

(0.645)

(6.45)

(64.5)

AREA, TOP COPPER AREA in (cm )

Figure 20. Thermal Resistance vs Mounting

Pad Area

1. Mounting pad area onto which the device is attached and

whether there is copper on one side or both sides of the

board.

2. The number of copper layers and the thickness of the

board.

3. The use of external heat sinks.

4. The use of thermal vias.

5. Air flow and board orientation.

6. For non steady state applications, the pulse width, the

duty cycle and the transient thermal response of the part,

the board and the environment they are in.

Fairchild provides thermal information to assist the

designer’s preliminary application evaluation. Figure 20

defines the R_θJAfor the device as a function of the top

copper (component side) area. This is for a horizontally

positioned FR-4 board with 1oz copper after 1000 seconds

of steady state power with no air flow. This graph provides

the necessary information for calculation of the steady state

junction temperature or power dissipation. Pulse

applications can be evaluated using the Fairchild device

Spice thermal model or manually utilizing the normalized

maximum transient thermal impedance curve.

Thermal resistances corresponding to other copper areas

can be obtained from Figure 20 or by calculation using

Equation 2 or 3. Equation 2 is used for copper area defined

in inches square and equation 3 is for area in centimeters

square. The area, in square inches or square centimeters is

the top copper area including the gate and source pads.

23.84

(0.268 + Area)

= 33.32 + ------------------------------------

(EQ. 2)

θ JA

Area in Inches Squared

154

= 33.32 + ---------------------------------

(EQ. 3)

(1.73 + Area)

Area in Centimeters Squared

FDD3672 Rev. A

PSPICE Electrical Model

.SUBCKT FDD3672 2 1 3 ;

CA 12 8 5.8e-10

Cb 15 14 6.8e-10

Cin 6 8 1.6e-9

rev May 2002

LDRAIN

DPLCAP

DRAIN

Dbody 7 5 DbodyMOD

Dbreak 5 11 DbreakMOD

Dplcap 10 5 DplcapMOD

RLDRAIN

RSLC1

DBREAK

RSLC2

ESLC

Ebreak 11 7 17 18 105

Eds 14 8 5 8 1

Egs 13 8 6 8 1

Esg 6 10 6 8 1

Evthres 6 21 19 8 1

Evtemp 20 6 18 22 1

DBODY

RDRAIN

EBREAK 18

ESG

EVTHRES

MWEAK

LGATE

EVTEMP

RGATE

GATE

It 8 17 1

MMED

MSTRO

RLGATE

Lgate 1 9 9.56e-9

Ldrain 2 5 1.0e-9

Lsource 3 7 4.45e-9

LSOURCE

CIN

SOURCE

RSOURCE

RLSOURCE

RLgate 1 9 95.6

RLdrain 2 5 10

RLsource 3 7 44.5

S1A

S2A

RBREAK

RVTEMP

S1B

S2B

Mmed 16 6 8 8 MmedMOD

Mstro 16 6 8 8 MstroMOD

Mweak 16 21 8 8 MweakMOD

VBAT

EGS

EDS

Rbreak 17 18 RbreakMOD 1

Rdrain 50 16 RdrainMOD 6.0e-3

Rgate 9 20 1.5

RVTHRES

RSLC1 5 51 RSLCMOD 1.0e-6

RSLC2 5 50 1.0e3

Rsource 8 7 RsourceMOD 9.5e-3

Rvthres 22 8 RvthresMOD 1

Rvtemp 18 19 RvtempMOD 1

S1a 6 12 13 8 S1AMOD

S1b 13 12 13 8 S1BMOD

S2a 6 15 14 13 S2AMOD

S2b 13 15 14 13 S2BMOD

Vbat 22 19 DC 1

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*98),3))}

.MODEL DbodyMOD D (IS=1.0E-11 N=1.05 RS=3.7e-3 TRS1=2.5e-3 TRS2=1.0e-6

+ CJO=1.2e-9 M=0.58 TT=3.75e-8 XTI=4.0)

.MODEL DbreakMOD D (RS=15 TRS1=4.0e-3 TRS2=-5.0e-6)

.MODEL DplcapMOD D (CJO=3.8e-10 IS=1.0e-30 N=10 M=0.60)

.MODEL MmedMOD NMOS (VTO=3.6 KP=3 IS=1e-40 N=10 TOX=1 L=1u W=1u RG=1.5)

.MODEL MstroMOD NMOS (VTO=4.3 KP=59 IS=1e-30 N=10 TOX=1 L=1u W=1u)

.MODEL MweakMOD NMOS (VTO=3.09 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=15 RS=0.1)

.MODEL RbreakMOD RES (TC1=9.0e-4 TC2=-1.0e-7)

.MODEL RdrainMOD RES (TC1=11.0e-3 TC2=5.0e-5)

.MODEL RSLCMOD RES (TC1=3.0e-3 TC2=1.0e-6)

.MODEL RsourceMOD RES (TC1=4.0e-3 TC2=1.0e-6)

.MODEL RvthresMOD RES (TC1=-3.5e-3 TC2=-1.5e-5)

.MODEL RvtempMOD RES (TC1=-4.3e-3 TC2=1.5e-6)

.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-5.0 VOFF=-3.5)

.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3.5 VOFF=-5.0)

.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=0.3)

.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=0.3 VOFF=-0.5)

.ENDS

Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global

Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank

Wheatley.

FDD3672 Rev. A

SABER Electrical Model

REV May 2002

template FDD3672 n2,n1,n3

electrical n2,n1,n3

{

var i iscl

dp..model dbodymod = (isl=1.0e-11,nl=1.05,rs=3.7e-3,trs1=2.5e-3,trs2=1.0e-6,cjo=1.2e-9,m=0.58,tt=3.75e-8,xti=4.0)

dp..model dbreakmod = (rs=15,trs1=4.0e-3,trs2=-5.0e-6)

dp..model dplcapmod = (cjo=3.8e-10,isl=10.0e-30,nl=10,m=0.60)

m..model mmedmod = (type=_n,vto=3.6,kp=3,is=1e-40, tox=1)

m..model mstrongmod = (type=_n,vto=4.3,kp=59,is=1e-30, tox=1)

LDRAIN

m..model mweakmod = (type=_n,vto=3.09,kp=0.05,is=1e-30, tox=1,rs=0.1)

DPLCAP

DRAIN

sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-5.0,voff=-3.5)

sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.5,voff=-5.0)

sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-0.5,voff=0.3)

sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=0.3,voff=-0.5)

c.ca n12 n8 = 5.8e-10

RLDRAIN

RSLC1

RSLC2

ISCL

c.cb n15 n14 = 6.8e-10

c.cin n6 n8 = 1.6e-9

DBREAK

RDRAIN

dp.dbody n7 n5 = model=dbodymod

dp.dbreak n5 n11 = model=dbreakmod

dp.dplcap n10 n5 = model=dplcapmod

ESG

DBODY

EVTHRES

MWEAK

LGATE

EVTEMP

RGATE

GATE

spe.ebreak n11 n7 n17 n18 = 105

spe.eds n14 n8 n5 n8 = 1

spe.egs n13 n8 n6 n8 = 1

spe.esg n6 n10 n6 n8 = 1

EBREAK

MMED

MSTRO

RLGATE

LSOURCE

CIN

SOURCE

spe.evthres n6 n21 n19 n8 = 1

spe.evtemp n20 n6 n18 n22 = 1

RSOURCE

RLSOURCE

S1A

S2A

i.it n8 n17 = 1

RBREAK

l.lgate n1 n9 = 95.6e-9

l.ldrain n2 n5 = 1.0e-9

l.lsource n3 n7 = 4.45e-9

RVTEMP

S1B

S2B

VBAT

res.rlgate n1 n9 = 9.56

res.rldrain n2 n5 = 10

res.rlsource n3 n7 = 44.5

EGS

EDS

RVTHRES

m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u

m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u

m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u

res.rbreak n17 n18 = 1, tc1=9.0e-4,tc2=-1.0e-7

res.rdrain n50 n16 = 6.0e-3, tc1=11.0e-3,tc2=5.0e-5

res.rgate n9 n20 = 1.5

res.rslc1 n5 n51 = 1.0e-6, tc1=3.0e-3,tc2=1.0e-6

res.rslc2 n5 n50 = 1.0e3

res.rsource n8 n7 = 9.5e-3, tc1=4.0e-3,tc2=1.0e-6

res.rvthres n22 n8 = 1, tc1=-3.5e-3,tc2=-1.5e-5

res.rvtemp n18 n19 = 1, tc1=-4.3e-3,tc2=1.5e-6

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod

sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod

sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod

sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1

equations {

i (n51->n50) +=iscl

iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/98))** 3))

}

FDD3672 Rev. A

SPICE Thermal Model

JUNCTION

REV May 2002

FDD3672

CTHERM1 TH 6 3.2e-3

CTHERM2 6 5 3.3e-3

CTHERM3 5 4 3.4e-3

CTHERM4 4 3 3.5e-3

CTHERM5 3 2 6.4e-3

CTHERM6 2 TL 1.9e-2

RTHERM1

RTHERM2

RTHERM3

RTHERM4

RTHERM5

RTHERM6

CTHERM1

RTHERM1 TH 6 5.5e-4

RTHERM2 6 5 5.0e-3

RTHERM3 5 4 4.5e-2

RTHERM4 4 3 10.5e-2

RTHERM5 3 2 3.4e-1

RTHERM6 2 TL 3.5e-1

CTHERM2

CTHERM3

CTHERM4

CTHERM5

CTHERM6

SABER Thermal Model

SABER thermal model FDD3672

template thermal_model th tl

thermal_c th, tl

{

cctherm.ctherm1 th 6 =3.2e-3

ctherm.ctherm2 6 5 =3.3e-3

ctherm.ctherm3 5 4 =3.4e-3

ctherm.ctherm4 4 3 =3.5e-3

ctherm.ctherm5 3 2 =6.4e-3

ctherm.ctherm6 2 tl =1.9e-2

rtherm.rtherm1 th 6 =5.5e-4

rtherm.rtherm2 6 5 =5.0e-3

rtherm.rtherm3 5 4 =4.5e-2

rtherm.rtherm4 4 3 =10.5e-2

rtherm.rtherm5 3 2 =3.4e-1

rtherm.rtherm6 2 tl =3.5e-1

}

CASE

FDD3672 Rev. A

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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR

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As used herein:

2. A critical component is any component of a life support

device or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body,

or (b) support or sustain life, or (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

result in significant injury to the user.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification

Product Status

Definition

Advance Information

Formative or In

Design

This datasheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

Preliminary

First Production

This datasheet contains preliminary data, and

supplementary data will be published at a later date.

Fairchild Semiconductor reserves the right to make

changes at any time without notice in order to improve

design.

No Identification Needed

Obsolete

Full Production

This datasheet contains final specifications. Fairchild

Semiconductor reserves the right to make changes at

any time without notice in order to improve design.

Not In Production

This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.

The datasheet is printed for reference information only.

Rev. H7

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FDD3672产品参数

型号:	FDD3672
Brand Name：	Fairchild Semiconductor
是否无铅：	不含铅
是否Rohs认证：	符合
生命周期：	Transferred
IHS 制造商：	FAIRCHILD SEMICONDUCTOR CORP
零件包装代码：	DPAK
包装说明：	TO-252AA, 3 PIN
针数：	3
制造商包装代码：	TO252 (D-PAK), MOLDED, 3 LEAD,OPTION AA &AB
Reach Compliance Code：	not_compliant
ECCN代码：	EAR99
HTS代码：	8541.29.00.95
风险等级：	3.09
雪崩能效等级（Eas）：	120 mJ
外壳连接：	DRAIN
配置：	SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压：	100 V
最大漏极电流 (Abs) (ID)：	6.5 A
最大漏极电流 (ID)：	6.5 A
最大漏源导通电阻：	0.028 Ω
FET 技术：	METAL-OXIDE SEMICONDUCTOR
JEDEC-95代码：	TO-252AA
JESD-30 代码：	R-PSSO-G2
JESD-609代码：	e3
湿度敏感等级：	1
元件数量：	1
端子数量：	2
工作模式：	ENHANCEMENT MODE
最高工作温度：	175 °C
封装主体材料：	PLASTIC/EPOXY
封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	NOT SPECIFIED
极性/信道类型：	N-CHANNEL
最大功率耗散 (Abs)：	135 W
认证状态：	Not Qualified
子类别：	FET General Purpose Power
表面贴装：	YES
端子面层：	Matte Tin (Sn)
端子形式：	GULL WING
端子位置：	SINGLE
处于峰值回流温度下的最长时间：	NOT SPECIFIED
晶体管应用：	SWITCHING
晶体管元件材料：	SILICON
Base Number Matches：	1

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